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Suggestions for a Zybo Z7-10 HDMI pass-through project

Go to solution Solved by elodg,



I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE.

Intention: To demonstrate whether  the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS.

Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor


Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used the diligent dvi2rgb and rgb2dvi IPs. Have used a PLL (not MMCM) to generate the ref_clk (125MHz is board input and the PLL produces the 200MHz clk required delay taps). I have attached my top level VHDL file which shows the connections. I have also attached the XDC file. Note that in the XDC I have changed the tmds_rx_clk frequency to 80MHz which is suitable for a HDMI data source with 720p resolution (else there will be Impl errors as the Z7-10 has a -1 speed grade FPGA). Bit stream was successfully generated without timing errors. The synth design is as shown below.


The design is not working after I have downloaded the bitstream. So the most important question is if the above makes sense?

If the above is rubbish, then what can I do to improve my design?

I just want to pass HDMI data from Rx port to the Tx port. Do I need to do some buffering of the pixel data (3 FIFOs for each channel with 8bits width, depth - I don't know )  before  connecting vid_pData from dvi2rgb to rgb2dvi? Else what would help? Any help/suggestions are appreciated.




Edited by dpaul
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HDMI_TX_HPD is input, HDMI_RX_HPD is output. See https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual#hdmi

Leave HDMI_TX_HPD unconnected, if not used.

Why don't you look at a demo we have on our Github: https://github.com/Digilent/Zybo-Z7-10-HDMI?

Debug your design by tying signals to LEDs or ILA modules. The flow is the following:

Sink (Zybo Z7) asserts Hot-Plug Detect -> confirm that HDMI_RX_HPD is tied high.

Source (whatever you have connected) queries the capabilities over DDC -> confirm that Digilent DVI appears as a secondary monitor on a PC for example.

Source begins transmitting video -> confirm that the Source actually enables the secondary monitor and drives a compatible resolution.

Sink locks onto the signal -> confirm that clk_wiz is locked and dvi2rgb/aPixelClkLckd goes high.

Video is decoded -> confirm dvi2rgb/VSync, HSync and VDE are toggling.

Video appears on output -> confirm hsync and vsync are correctly timed for the expected resolution.

Edited by elodg
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We don't have a Z7 board, but we do have Arty Z7 and Zybo Z7. Check the HDMI section of the Zybo Z7 reference manual for auxiliary signals. Everything you described is sound, it is just missing HPD. Hot plug detect needs to be driven by RX high, so that your laptop can read the DDC and detect a display. Also, if the board has buffers, muxes on the data path, there might be an enable signal needed too.

Edited by elodg
Noticed Zybo Z7 in the title.
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Resurrecting this thread again....

I am now driving hpd_tx and hpd_rx now high. But I still don't get anything on my display.


I know that others have done it, have read through their threads, but still can't understand what I am doing wrong.

I am constraining the cores to 80MHz for 720p resolution (as I am using -1 speed grade FPGA, ZyboZ7-10). My source, laptop display I have set to 1280x720. The display monitor is Fujitsu which I think should be capable of displaying resolution.

For the clock generator I am using a PLL whose i/p is 125MHz and supplies the refclock of 200MHz to the dvi2rgb core.

Further suggestions will be very helpful.







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I looked at your constraints file and one thing puzzles me. You've constrained the clock to be a higher frequency than the 'standard' clock frequency in the file. In the dvi2rgb documentation there is this info on the TMDS clock constraint:

The TMDS clock input Clk_p/n is constrained in the IP to the maximum DVI clock frequency, 165 MHz. On some architectures this might result in timing impossible to meet. Depending on the application, if a lower pixel clock frequency is acceptable, the clock can be constrained on top-level, which will override the IP-internal constraints. 
For example, to constrain the design for 720p resolution (74.25 MHz), calculate the clock period (13.468 ns), and add the following to a project XDC file to constrain the clock on the top-level input port: 


create_clock -period 13.468 -waveform {0.000 5.000} [get_ports hdmi_rx_clk_p]

I've just been experimenting with the Vivado TPG and found that if I didn't use that frequency in concert with the rgb2dvi component things didn't work.

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There were 3 changes.

1. HDMI_TX_HPD is input, HDMI_RX_HPD is output. Leave HDMI_TX_HPD unconnected, if not used.

2. I was constraining hdmi_rx_clk_p_i to 80MHz, but then I changed it to 74.25MHz (create_clock -period 13.468 .......). I think even if I constrain it to 80MHz, it would  still work!

3. Then I was making a stupid mistake and I think it was the biggest bottleneck. I was making a typo error where I was connecting some signal of std_logic_vector(2 downto 0) to another of std_logic_vector(0 to 2).

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