Genesys2 demo project

[zygot]

Where can I get the source for the demo design that is shipped with the Genesys2 board?

[zygot]

Hey Tom,

I have Vivado 2015.4 Design edition and as you mention I can't use the board design from the Vivado 2014 edition. I do have the Webpack 2014 edition and using it fails to create the project properly or create a usable board design. I'm doing all of this on Centos which is a very painful process. It's not reasonable for me to install yet another Vivado edition so what can I do to recreate this project?

BTW. You need to provide a demo that doesn't require temporary third party license files so that at least SOMETHING can be used as a baseline that won't become unusable after a few months. You also need to figure out how to allow your customers to re-create sources, such as the board design, from scratch in a way that avoids all of the issues of Vivado version incompatibility nonsense. I have a board and no good starting point from which to do development.

A much preferred option would for you to provide a demo that has ALL sources in VHDL or Verilog. This will eliminate all of the head trauma for your and me. It's the only way that I know of to compile a project that is independent of the tool set version. At first glance it seems easier to develop a design with a soft processor/SDK core but since all of your customers aren't using the same tools the "quick" path becomes a nightmare for everyone. The fact that Vivado 2015 can't use a board design created in Vivado 2014 should be telling you something.

[zygot]

Well, you're last question is my main issue. I use webpack versions because I just can't afford to buy licenses for all of the FPGA vendors tools that I use every year. Who can? So why aren't you releasing demo projects that work with the free tool versions? I've been doing projects using the XC7K325tffg900 part for years using Vivado 2014.2 on Windows  ( the last "full seat" version available for the KC705 ). I also have been doing projects on Centos using the free Vivado 2015.4 version and the XC7K325tffg900 license that I got when I bought the Genesys2 board from Digilent to do projects for that board. Very few individuals can afford ( and a lot of small companies refuse ) to pay Xilinx $2500, Altera $3000, Lattice $1000, Microsemi etc., every year for full seat versions of tools. The whole point of device specific licenses is to allow anyone access to a limited number of tool versions for a specific board like the Genesys2 node-locked to one installation of tools on one computer.

As to RGMII, it's just a DDR version of GMII using half the data bits. You don't need a "core" just some effort arranging standard UNISIM library components to get the timing correct. SGMII is a lot more troublesome ( just in case you're planning a new board using that interface...). Of course the PHY on Genesys2 COULD have used a GMII interface had any thought been given to the design. (Here's where I'd like to go on and on about Digilent's poor design decisions for the Genesys2 board but instead I'll compliment you for the one VERY GOOD decision that you made: the DisplayPort implementation is wonderful though not particularly for video purposes as far as I'm concerned.)

With regard to soft uP cores like NIOS or Microblaze I understand why people use them. Altera and Xilinx make it easy to throw together a nice demo using their IP cores for a lot of functionality. Once you've tried maintaining lots of projects through many tool updates the initial savings in time becomes insignificant as almost every new version of tools breaks either the hardware or software and often both. It took me quite some time to create a stand-alone external SDRAM controller for the Spartan 6 and Kintex devices but now I have HDL code that survives too versions. Sometimes it makes sense to use Microblaze but for a lot of projects it's mostly a lot of superfluous work that needs maintenance. Are you happy with the level of support that you've been able to provide for the Genesys2 and Nexys Video products? I can guarantee you that few of your customers are.

 

[sbobrowicz]

Hi Zygot,

I hear you, and agree with a lot of what you are saying. But we cannot ignore block diagrams, microblaze, and other IP cores: they provide too much value for our customers. It is very difficult to use many of the components on the Genesys2 in a meaningful way without using an IP core (DDR3, Ethernet, Displayport are examples). On top of that, in many cases properly designing your system around a microblaze processor(s) reduces design-time and results in a project that is more readily adapted to meet future requirements. This type of approach can turn design-time from weeks into hours.

Understanding that we can't turn away from IP blocks entirely, here are my comments on your other suggestions:

-When used to generate a project that does not contain a block diagram (even if it does contain IP blocks), tcl scripts actually tend to increase version compatibility. This is because project files cannot be opened in earlier versions, however a tcl script will generate a project for whatever version it is being run in. There are cases when a project creation tcl script can break across tool versions, but this is not as common as you might think. They also greatly increase a project's ability to be properly version controlled, which is necessary for us to be able to successfully maintain them (as is true with all software).

-tcl scripts that are used to generate block diagrams are version specific. This is very unfortunate and what is behind the headaches you have experienced with our demos. We are implementing a plan to mitigate this problem. First, we plan to update all block diagram containing projects on our github to version 2015.4. Once we achieve this, we will maintain these projects by systematically updating them to the "even" versions of Vivado as they come out. This means that when 2016.2 comes out, we will go through and update each project, handling any conflicts that occur with new versions of IP cores. This will ensure that our projects are all usable in recent versions of the tools, and also that people who only have access to earlier versions of tools (perhaps due to license expiration) can revert the repo and use an older version of the project. Choosing to only do the even versions (.2 and .4 releases) is a necessary compromise to make this task achievable for us. I'd like to hear your comments on this plan, specifically if you think this would have addressed the problems you encountered.

-When it makes sense, creating a pure HDL project can increase portability between tool versions and hardware (which is particularly useful to us). We do this when we can, typically to highlight simpler onboard components like GPIO, UART, and VGA. But when a project begins to need external memory or have complex state requirements, it begins to make more sense to teach people to do it the easier way, with microblaze. To assist those that prefer to design purely in HDL, we are putting together a library of re-usable HDL components on our github (it's not ready yet). This will contain many of the "reference components" found on our old website, and a revamped collection of useful components such as I2C controllers, UART controllers, etc.

-I hate it when we are forced to use paid cores, and we do whatever we can to get around this when possible. On the Genesys2, we currently require paid cores to use the USB-OTG, Displayport, and ethernet. Good news on the USB-OTG front, we are about to release an open source USB device core and some example microblaze software to go with it. For ethernet, all we need is a functional GMII to RGMII IP core and that will allow us to use the free ethernet lite core instead of the paid "ethernet subsystem" core. Vivado already ships with such a core, but for some reason it only lists "zynq" devices as supported. We are looking for a way around this. Display port will be the toughest nut to crack, though I recall Hamster (on this forum) mentioning he has successfully gotten display port output functioning in some capacity. 

-Regarding ISE compatibility, we made the decision to just focus on releasing Vivado projects for the products that are supported in both tools (Nexys4-DDR, Nexys Video, Genesys 2, ZYBO and ZedBoard). We feel pretty strongly that Vivado is a viable replacement to ISE in all regards, with the exception of those who require the schematic capture tool for teaching purposes (though IPI libraries are getting close to being able to replace that need too). That said, you bring up a good point about our lack of UCFs, so I will find some resources to put these together this summer. 

You mentioned that Vivado 2014.4 does not work with your license that unlocks 2015.4. According to this, that should not be the case:

http://www.xilinx.com/support/answers/33770.html

A node locked license is supposed to unlock all versions of the tools that are released prior to the "version limit" date. Are you certain that the "Design Edition" of 2014.4 was installed on your machine? If it was the webpack version, targeting the genesys2 will not work, even with a license installed. 

 

[TommyK]

Hi guys,

I've updated the Genesys2 user demo to work with 2015.4. I don't have much say in how we are packaging the projects up, but I've told some higher ups.

 

Thanks,

Tommy

[zygot]

Thanks JColvin.

Let me apologize for re-iterating past suggestions but apparently no one at Digilent is listening.

TCL scripts and board designs simply don't survive across Vivado versions. Customer's can't use arbitrary versions of Vivado because of node-locked licensing( particularly for Genesys2) and other issues . Even though Vivado says that you can open or create a project created by an earlier version tools, save it and then open the project with the version of Vivado that you need to use I haven't yet to find that this is the case. The current GENESYS2 TCL source using Vivado 2014.4 fails because I don't have a license for the FPGA part. The current hdmi demo TCL scripts fail because it was created in Vivado 2015.3 and I don't have that version installed anywhere. NONE of your demo code has produced a working project or block design using the tool versions available to me.

The only way that I can see Digilent's customers being happy and Digilent's developer's maintaining their sanity is to get off the Vivado version treadmill.

Here's how to do it:

- Don't use tcl scripts to build projects or anything else

- Don't use a Vivado 'block design' in demo projects

- Do use HDL for everything except basic IP elements such as PLL, MCMM, block ram, etc. and use the generated HDL in the code base. Do read the HDL guidelines so that you can use all HDL instead if IP coregen projects for Xilinx IP.

- If you need Xilinx IP for things like an Ethernet MAC make it clear that the customer has to request an evaluation license to build the demo. By the way, you don't need a MAC to use the Ethernet PHY hose to demonstrate that the hardware is functional....

- DO use an HDL for the toplevel and all other source code.

I know that this works because I've been doing FPGA development for 20 years and have learned how limit the damage every new release of tools brings. This isn't just a Xilinx issue other vendors are just as bad or worse. Yes, it will require a bit more work to 'roll' your own code but you will end up with projects that survive tool versions. Even better you won't have to care about your customer's tools version or environment.  I still use ISE unless I'm doing prototyping or HAVE to use Vivado; and will continue until Xilinx no longer makes devices supported by ISE. Digilent doesn't even provide a ucf. file for new boards.

regards,

Zygot 

[JColvin]

Hi zygot,

I have contacted Sam to let him know that you are still waiting on an update.

Thank you for your time,
JColvin

[zygot]

it's been 5 months since I started this post and I still am not able to re-create the basic demo for the Genesys2 board. As of today the only source that you provide requires Vivado 2014.4 with a license for the XC7K325T device. My licence works with Vivado 2015.4 which is the version that I am using. The TCL scripts you provide cannot create either a complete Vivado project or a board design. I see 2 possible paths to success.

You can update the Genesys2 resource website with TCL scripts that work with Vivado 2015.4 or you can make available a fully working Vivado 2014.4 project that I can open with Vivado 2015.4. Please give me a fighting chance.

This is the first board the I've purchased from Digilent that is simply not supported adequately.

[dakefeng]

zgyot,

I am working on it right now, and what do you want as a simplest demo? I will see if I can make one. Are you using Vivado 2015.4?

Besides, I am still waiting for the board definition file for genesys2.. I think when we have that it would be a lot easier to start a new project.

Best,

Dake

[zygot]

Dake,

Thanks for your comments. My problem is that I use (mostly ) 1 Windows box and 1 Linux box for development and each has way too many versions of Xilinx (10!) and Altera tools installed already. All of them are necessary due to node locked license features or other reasons. I just can't spend the time to install any arbitrary version of toolset every time I buy a new board. I don't want to go back and fix every old project that has bee broken by version incompatibility. It's insane. Of course it's possible to create designs that are TCL script free, block diagram free and use minimal IP making it  easy to migrate to any version of tool that supports your device. You just have to make the decision to do it. I've been doing this for many years. Competitors in Digilent's FPGA board space do it. Why would anyone NOT want to do more with less work and aggravation?

Sam,

If you can figure out how to create version independent Vivado board designs with TCL scripting that I can use with the tools I have then great. All I know is that I can't create a usable project for the Genesys 2 board from your source and I don't want to spend weeks combing through all those scripts trying to resolve problems. I even have a full Vivado 2014.2 licensed for Kintex available to me... but it's as useless as the latest version. This is nuts! I've been buying boards from Digilent for many years and you have HDL for most of the interfaces already done. At least provide a simple design with a top level in HDL, no soft processor, no SDK, no block diagram, no headaches that run the external memory, HDMI, Adept interface, UART, etc. You'll have less work. I'll have less work. You'll be happier. I'll be happier. Is that such a bad thing?

 

[sbobrowicz]

Hi Zygot,

BTW. You need to provide a demo that doesn't require temporary third party license files so that at least SOMETHING can be used as a baseline that won't become unusable after a few months.

Agreed. We will post a version of this project with no display port and the ethernetlite core. 

The issue is the source provided by Digilent and the decision by Xilinx to release tool updates that break any project that relies on any of their IP/SDK created by earlier versions of their tools

This is a problem with our Vivado IPI (block diagram) projects we are currently investigating as we transition our Vivado project hosting to Github. The trouble here is finding a balance between hosting projects that are lightweight and version-controllable vs. projects that support multiple Vivado versions. The block diagrams can be hosted very nicely as TCL scripts, but they can only be generated in a single version of Vivado. The solution we are currently leaning towards is to use block diagram TCL scripts, and systematically update them for all microblaze and zynq projects every time a new version of Vivado comes out. Customers would then expect all projects hosted by us to be on the newest version, but older versions of projects could be obtained by reverting to previous versions of the Git repo. What do you think about this approach?

[dakefeng]

Hey Tom,

I have Vivado 2015.4 Design edition and as you mention I can't use the board design from the Vivado 2014 edition. I do have the Webpack 2014 edition and using it fails to create the project properly or create a usable board design. I'm doing all of this on Centos which is a very painful process. It's not reasonable for me to install yet another Vivado edition so what can I do to recreate this project?

BTW. You need to provide a demo that doesn't require temporary third party license files so that at least SOMETHING can be used as a baseline that won't become unusable after a few months. You also need to figure out how to allow your customers to re-create sources, such as the board design, from scratch in a way that avoids all of the issues of Vivado version incompatibility nonsense. I have a board and no good starting point from which to do development.

A much preferred option would for you to provide a demo that has ALL sources in VHDL or Verilog. This will eliminate all of the head trauma for your and me. It's the only way that I know of to compile a project that is independent of the tool set version. At first glance it seems easier to develop a design with a soft processor/SDK core but since all of your customers aren't using the same tools the "quick" path becomes a nightmare for everyone. The fact that Vivado 2015 can't use a board design created in Vivado 2014 should be telling you something.

What I did was download the 2014.4 vivado design edition and start to work. I can understand how they struggle with the upgrading of the development tools, since I had great headache from the ISE... The nightmare is always from different version of IP core, and sdk version confliction.

BTW I do not know how long it would take to write a demo that has all source in VHDL to support so many devices without using the block diagram things, and unfortunately, you will face similar problem of IP core version problems too.

Besides, I do not think an early version of vivado matters. Unless you have some special requirements from the latest version of it. That is my personal opinion. At least, you can start with it.

Good luck,

Dake

[zygot]

LariSan,

I should have been more specific. I am using Vivado 2015.4 Design Edition ( the latest available ) with a license from the voucher provided in the Genesys 2 box. The license for the correct Kintex part is not the issue. The version of Vivado should not be the issue. The issue is the source provided by Digilent and the decision by Xilinx to release tool updates that break any project that relies on any of their IP/SDK created by earlier versions of their tools. Unless you change your policies there is no escape from being sucked into the giant version incompatibility hole. I have the same problem with Altera. Everyone, mostly Digilent, will be better off if you develop IP agnostic code; at least for the purposes of proving that your hardware does indeed function. Yes, using some IP such as external memory controllers and ARM based hard processor cores are unavoidable; but these are relatively manageable. The big headaches start with using a Vivado board design as a source in your design projects. I not suggesting that no one ever use that whole IP ecosystem ( I do but only when unavoidable ) but that it's not appropriate for everything. I have projects that I've developed that I can build with ISE or any version of Vivado with minimal effort.
Please give us poor customers something that doesn't require hours of installations/troubleshooting to use in exchange for our hard earned money.

[LariSan]

thanks for your quick reply... but....did I read this correctly? I have to use buy a full Vivado 2014.4 license to do anything with the example code? Is this a new trend? I've really become frustrated having to chase down documentation and supporting files in order to get started with my last two purchases of rather expensive FPGA boards.

The Genesys2 should include a voucher for the full Vivado Design Edition (it's included). 

[TommyK]

Hi Dakefeng,

I can't tell you how long I've struggled against Xilinx licenses, but I'm glad you figured it out!

Good luck!

Tommy

[dakefeng]

problem solved, I mistakenly put wrong hostid when I was generating the hardware evaluation license.

[dakefeng]

Thanks tom. I downloaded the hardware_evaluation license from xilinx and installed it. Now I can see it under vivado license manager. Well, if I clear the checkbox of hide free-built-in license I can still see there is another design_link license entry of display port.

But the demo in vivado 2014.4 still only see the design_link license, even I recreate the project with that tcl script. I was trying to get rid of the xilinx.lic under core_licenses directory to force vivado only load from the downloaded license, but this time it says no license found.

And idea on this?

Many thanks,

Dake

[TommyK]

Hi Dakefeng,

That's something I forgot to mention. You will have to download licenses for the Displayport IP as well as the TEMAC adapter. You can et evaluation licenses on Xilinx's website, but a faster option would be to use the already generated hardware wrapper found on the Wiki,

There is a tutorial describing how to do it here!

 

Regards,

Tommy

[dakefeng]

It seems to be license problem, the displayport license is design linking. How can I have it solved? many many thanks.

[dakefeng]

Hi everyone, I am trying to regenerate the bitstream but I am keeping get error like this:

 Command failed: This design contains one or more cells for which bitstream generation is not supported:
system_i/video/displayport_0/inst/support_inst/core_top_inst/dport_link_inst (displayport_v5_0_txlink_top)
system_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/bd_0_eth_mac_0_core (tri_mode_ethernet_mac_v8_3)

    while executing
"write_bitstream -force system_wrapper.bit -bin_file"

I am using vivado 2014.4. Thanks!

 

[TommyK]

Hi Zygot,

I'm sorry I phrased that wrong. I believe that you need Design edition to target the FPGA on the Genesys2, and the license should work on all versions older than the one you have installed. I could be wrong though. All of the code is included in the zip file. It is all done in SDK, so the source files are all included in the SDK folder. The only thing you should need 2014.4 for is to generate the project/block diagram. Once it is generated, you could try upgrading it to Vivado 2015, but once again I'm not sure how nice it will play with the custom IPs. We're working on putting out more support materials for the Genesys2 right now, so hopefully this wont be a problem in the future.

 

Hope this helps,

Tommy

[zygot]

thanks for your quick reply... but....did I read this correctly? I have to use buy a full Vivado 2014.4 license to do anything with the example code? Is this a new trend? I've really become frustrated having to chase down documentation and supporting files in order to get started with my last two purchases of rather expensive FPGA boards.

[TommyK]

Hi again,

I just uploaded the files needed to generate the source for the demo design for the Genesys2. There is a readme file within the zip folder that should guide you through it. You must use Vivado 2014.4 (not the Webpack version). You can find the zip file here.

 

Good luck!

Tommy

[TommyK]

Hi guys,

It is currently unavailable, but we will hopefully get it posted soon. I will let you know,

 

Thanks,

Tommy

[dakefeng]

I ordered this board and I want it too. If there is any reasons it is not available, please let me know as well.

 

Many thanks.