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ahmed nasser

Generating bitstream (programming file)

Question

I am using Nexys4DDR board, xc7a100t-1csg324.

While using ISE 14.5 or ISE 14.7, synthesize and implementation are done without errors. But, while generating the bitstream to configure the FPGA chip, this step is stucked (i.e., Generating bitstream is running and never stop) without any error.

Maybe with the same design without any modification, this step is completed normally but the many times it is not.

please someone help me with this point.

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6 answers to this question

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Hi Ahmed,

I can try to help, but it is difficult when all I have to work with is a screenshot. It looks like you have a few warnings in your Synthesis and Implementation steps. These warnings might have an explanation as to why the Xilinx ISE is getting stuck trying to write a bitstream. Could you provide any more information on these warnings or any console messages that might stand out?

 

Thanks,

Tommy

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Hi Tommy,

The warnings are: 

HDLCompiler:89 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 103: <fft2048> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:439 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 189: Formal port control0 of mode inout cannot be associated with actual port control0 of mode out
WARNING:HDLCompiler:439 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 193: Formal port control of mode inout cannot be associated with actual port control of mode in
WARNING:Xst:2677 - Node <XLXI_14/rf> of sequential type is unconnected in block <system>.
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
   'XLXI_8/blk00000071/blk00000093/RAMB18E1' of type RAMB18E1 has been changed
   from 'VIRTEX6' to '7SERIES' to correct post-ngdbuild and timing simulation
   for this primitive.  In order for functional simulation to be correct, the
   value of SIM_DEVICE should be changed in this same manner in the source
   netlist or constraint file. For additional information on retargeting this
   primitive to 7SERIES, please see
   http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migratio
   n.pdf.
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
   'XLXI_8/blk00000071/blk00000094/RAMB18E1' of type RAMB18E1 has been changed
   from 'VIRTEX6' to '7SERIES' to correct post-ngdbuild and timing simulation
   for this primitive.  In order for functional simulation to be correct, the
   value of SIM_DEVICE should be changed in this same manner in the source
   netlist or constraint file. For additional information on retargeting this
   primitive to 7SERIES, please see
   http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migratio
   n.pdf.
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
   'XLXI_8/blk00000095/blk000000b7/RAMB18E1' of type RAMB18E1 has been changed
   from 'VIRTEX6' to '7SERIES' to correct post-ngdbuild and timing simulation
   for this primitive.  In order for functional simulation to be correct, the
   value of SIM_DEVICE should be changed in this same manner in the source
   netlist or constraint file. For additional information on retargeting this
   primitive to 7SERIES, please see
   http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migratio
   n.pdf.
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
   'XLXI_8/blk00000095/blk000000b8/RAMB18E1' of type RAMB18E1 has been changed
   from 'VIRTEX6' to '7SERIES' to correct post-ngdbuild and timing simulation
   for this primitive.  In order for functional simulation to be correct, the
   value of SIM_DEVICE should be changed in this same manner in the source
   netlist or constraint file. For additional information on retargeting this
   primitive to 7SERIES, please see
   http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migratio
   n.pdf.
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001b9' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ba' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001bb' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001bc' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001bd' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001be' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001cf' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001d0' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001e9' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ea' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001eb' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ec' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ed' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ee' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk000001ff' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000200' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000219' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000021a' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000021b' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000021c' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000021d' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000021e' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000022f' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000230' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000249' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000024a' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000024b' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000024c' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000024d' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000024e' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk0000025f' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000260' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000707' has unconnected output
   pin
WARNING:NgdBuild:443 - SFF primitive 'XLXI_8/blk00000716' has unconnected output
   pin
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_47<13> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Where the XLXI_8 is the FFT logic ipcore.

Thanks,

A.Nasser

 

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Hi Ahmed,

This is a tough question for me to answer since it seems to be more a problem with Xilinx's software.  Have you tried asking their support team? I've asked around the office and nobody has come across this before. Unfortunately, the Write Bitstream operation doesn't produce any useful log files. Since you are working with a 7-Series FPGA, I would definitely switch over to Vivado, which is free and much more robust. This would probably solve your problem. Let me know if you need any more suggestions!

 

Thanks,

Tommy

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