Make the system clock external

[Billel]

Hi every body

I’m working on project where I need to make the system clock externel, start with this simple project. I want to implement a selector between two clocks ( clk and clk1)  to the output clk_out0, where clk is the system clock and clk1 is a simple signal that I emulated in this project using the sw1 of the nexys4 ddr fpga board.  I use the sw0 of the board to switch between the two clocks.

 when I select the clk1 ,that comes from sw0, the clk_out0 works perfectly , Unfortunately,  when I select the system clock I get a steady signal of 1.8 V ,  the    clk_out1 ,which is supposed to be the system clock, is also at 1.8V.

Can anyone tell me what is wrong in the program?

here is the vhdl program:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity padd is

    port (

        clk:in std_logic;

        clk1:in std_logic;

        selector:in std_logic;

        clk_out1 : out  std_logic;

        clk_out0 : out  std_logic

        );                     

    end padd;

architecture padd of padd is

begin

  process(clk)

  begin

if selector ='0' then 

                            clk_out0<= clk;

                    else    clk_out0<= clk1;

                    end if;

  end process;

clk_out1<= clk;

end padd;

 

and this is the xdc configuration

Thanks.

[dpaul]

@Billel

I don't think MUXing of clocks is done as we  doing it as we do it for signals (experienced members correct me if I am wrong).

Don't do such a thing as described above for clocks, they can cause glitches and and all kind of nasty stuff.

Use the Xilinx primitive BUFGMUX.

Please see UG472 : https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

[D@n]

@Billel,

To add to what @dpaul said, the reason why you are getting a constant "1" output is because you are setting the clock on every positive edge.

If you want to output a clock, Xilinx recommends using the ODDR module.  I've tried it often, and it works quite well.  Using the clock, set the output to '1' on the rising edge, and '0' on the negative edge.

Dan

[Billel]

Thank you for every one

What is astonished for me is why clk_out1<= clk; does not work. It is supposed to be the image of clk.

[DigitalConfig]

instead of tying a port to a port try tying input ports to signals then either tie the output port to the signal or selecting the signal to the output port

hope this helps,

DC

[DigitalConfig]

also have you considered an asynchronous or synchronous divide by?

DC