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Foisal Ahmed

Basys3 Boards Problem

Question

Hi,

I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board.

But the problem is that now it is not working for another three new  Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator.

Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it.

Thanks

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Hi@jpeyron

Thank you for your kind reply. Yes, all six devices are Artix-7 devices basys 3's (3 devices are four month old and 3 devices that not work properly are 1 week old). Not any error in vivado yet. It correctly synthesized and implemented. But whenever I want to download the program in the Artix-7 devices basys 3's they showing the problem which I have mentioned in my post.

Thanks

Edited by Foisal Ahmed

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HI @JColvin,

Thanks a lot for this valuable link. In the problem, I have another problem after analyzing that the above problem only shows when I have changed XDC file by manually. To take ring oscillator frequency every time I have to move LUT location changing like BEL, slice etc. Some location does not reset but some location resets automatically. Besides these, In my design have some timing slack which I have not removed yet.

 

Thanks

Foisal

 

Edited by Foisal Ahmed

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Hi @Foisal Ahmed,

I was able to generate a bitstream with your verilog files and xdc's. Are you saying the project does not work on the board due to the lut warnings? 

[Common 17-165] Too many positional options when parsing 'LUTLP-1>', please type 'get_cells -help' for usage info.

Here is a xilinx forum thread the should help with this issue.

thank you,

Jon

 

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