dpaul Posted May 10, 2018 Share Posted May 10, 2018 Hi, I am trying to use the DVI-to-RGB (Sink) 1.9 IP Core. In it is the pRst input, which is defined as per the spec "Active-high reset synchronous with PixelClk. Configurable polarity." How do I generate this signal? Will it be sufficient if I feed the aRst input synced with PixelClk (output clk from the IP) to serve as pRst? For now I have just set it to '0', but is it the right thing to do? Thanks. Link to comment Share on other sites More sharing options...
jpeyron Posted May 10, 2018 Share Posted May 10, 2018 Hi @dpaul, Here is a forum thread the has a screen shot of the block design as well as xdc information that should be useful for your project. cheers, Jon Link to comment Share on other sites More sharing options...
dpaul Posted May 13, 2018 Author Share Posted May 13, 2018 @jpeyron, thanks for the link! It helped me to solve the problem. The tmds _rx_clk must be contained for < 80MHz for successful bitstream generation if one is using Zybo Z7-10 (because of speed grade -1) . But it is another issue that my design is not working! I have opened a thread for it named hdmi_pass. Link to comment Share on other sites More sharing options...
jpeyron Posted May 14, 2018 Share Posted May 14, 2018 Hi @dpaul, Glad the link helped. thank you, Jon Link to comment Share on other sites More sharing options...
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dpaul
Hi,
I am trying to use the DVI-to-RGB (Sink) 1.9 IP Core.
In it is the pRst input, which is defined as per the spec "Active-high reset synchronous with PixelClk. Configurable polarity."
How do I generate this signal? Will it be sufficient if I feed the aRst input synced with PixelClk (output clk from the IP) to serve as pRst?
For now I have just set it to '0', but is it the right thing to do?
Thanks.
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