hamster Posted November 21, 2015 Share Posted November 21, 2015 Hi, I've been using the constraints file from https://reference.digilentinc.com/_media/genesys2:genesys2_h.zip and from debugging the pins for JA seem to be wrong set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] should really be set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] The low half seem to have the same problem too. The _p is connected to pin 1, 3, 7 or 9, and the _n is connected to pins 2,4,8 or 10 Looks like JB is the same too! Mike Link to comment Share on other sites More sharing options...
cristian.ignat Posted December 4, 2015 Share Posted December 4, 2015 Hi, Now it's ok. Cristian Link to comment Share on other sites More sharing options...
mwingerson Posted November 25, 2015 Share Posted November 25, 2015 that is weird, I just checked the schematic and it appears to agree with the XDC file. I'll email our layout guy to double-check the schematic and I'll try to confirm your findings on a genesys2 Link to comment Share on other sites More sharing options...
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hamster
Hi,
I've been using the constraints file from https://reference.digilentinc.com/_media/genesys2:genesys2_h.zip and from debugging the pins for JA seem to be wrong
set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]
set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
should really be
set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]
set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
The low half seem to have the same problem too. The _p is connected to pin 1, 3, 7 or 9, and the _n is connected to pins 2,4,8 or 10
Looks like JB is the same too!
Mike
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