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Arty_bsd problem in implementation


MPS

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Hi.  I am getting acquainted with my new Arty.   From the Arty Resource Center wiki I have successfully completed the General I/O Demo and the XADC Demo.  However, I have encountered a problem with the Microblaze Base System Design demo arty_bsd.xpr 

I believe I have been following instructions correctly.  "Run Synthesis" completes without error.  However, "Run Implementation" reports the following errors:

  •  
    [Place 30-58] IO placement is infeasible. Number of unplaced terminals (36) is greater than number of available sites (0).
    The following Groups of I/O terminals have not sufficient capacity:
    IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 36 sites.
        Term: shield_dp0_dp19_tri_io[0]
        Term:  shield_dp0_dp19_tri_io[1]
        Term:  shield_dp0_dp19_tri_io[2]
        Term:  shield_dp0_dp19_tri_io[3]
        Term:  shield_dp0_dp19_tri_io[4]
        Term:  shield_dp0_dp19_tri_io[5]
        Term:  shield_dp0_dp19_tri_io[6]
        Term:  shield_dp0_dp19_tri_io[7]
        Term:  shield_dp0_dp19_tri_io[8]
        Term:  shield_dp0_dp19_tri_io[9]
        Term:  shield_dp0_dp19_tri_io[10]
        Term:  shield_dp0_dp19_tri_io[11]
        Term:  shield_dp0_dp19_tri_io[12]
        Term:  shield_dp0_dp19_tri_io[13]
        Term:  shield_dp0_dp19_tri_io[14]
        Term:  shield_dp0_dp19_tri_io[15]
        Term:  shield_dp0_dp19_tri_io[16]
        Term:  shield_dp0_dp19_tri_io[17]
        Term:  shield_dp0_dp19_tri_io[18]
        Term:  shield_dp0_dp19_tri_io[19]
        Term:  shield_dp26_dp41_tri_io[0]
        Term:  shield_dp26_dp41_tri_io[1]
        Term:  shield_dp26_dp41_tri_io[2]
        Term:  shield_dp26_dp41_tri_io[3]
        Term:  shield_dp26_dp41_tri_io[4]
        Term:  shield_dp26_dp41_tri_io[5]
        Term:  shield_dp26_dp41_tri_io[6]
        Term:  shield_dp26_dp41_tri_io[7]
        Term:  shield_dp26_dp41_tri_io[8]
        Term:  shield_dp26_dp41_tri_io[9]
        Term:  shield_dp26_dp41_tri_io[10]
        Term:  shield_dp26_dp41_tri_io[11]
        Term:  shield_dp26_dp41_tri_io[12]
        Term:  shield_dp26_dp41_tri_io[13]
        Term:  shield_dp26_dp41_tri_io[14]
        Term:  and shield_dp26_dp41_tri_io[15]


     

 

 

 

I am using Vivado 2015.2. Any assistance would be appreciated!

 

 

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3 answers to this question

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Hey MPS,

I've spoken to our applications team and it appears that this is the result of an issue with the current board file available for the Arty. We are working on making the updated board file available as soon as possible, but it may take until the other side of the holiday weekend before final updates are made to the project page. Sorry for the trouble, but please keep an eye on the project page to see when the update becomes available.

Regards, 

Nate

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Hello

I just received my ARTY and try arty_bsd with vivado 2015.4

Vivado start with an upgrade from 2015.2 to 2015.4 and ends up with this:

  • Vivado Commands
  • upgrade_ip [get_ips {system_microblaze_0....
  • [IP_Flow 19-3298] Detected external port differences while upgrading IP 'system_axi_gpio_led_0'. These changes may impact your design.
  • [BD 41-1165] The interface pin 'GPIO2' with bus definition 'xilinx.com:interface:gpio:1.0' is not found on the upgraded version of the cell '/axi_gpio_led'. Its connection to the interface net 'axi_gpio_led_GPIO2' has been removed.
  • blabla.....

There are 34 critical warning while upgrading the IPs...... Obviously, it does impact with the rest of the process and cannot generate bitfile :-(

So please add this info to the ticket 

 

Best Regards

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