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zybo hdmi out, tmds signal errors


nasajohnc

Question

Hi, I'm trying to build the "zybo hdmi out" project in Vivado 2016.4

The tcl script runs good except it has a problem with the "rgb2dvi" IP and adding the TMDS signals. And after the script has finished the block diagram does not show the TMDS ports.

Can anyone see what is wrong here?

See tcl console output below:

 

source create_project.tcl
# set proj_name "hdmi-out"
# if {[info exists ::create_path]} {
#     set dest_dir $::create_path
# } else {
#     set dest_dir [file normalize [file dirname [info script]]]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in C:/git/Zybo-hdmi-out/proj
# cd $dest_dir
# set part "xc7z010clg400-1"
# set brd_part "digilentinc.com:zybo:part0:1.0"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" $part $obj
# set_property "board_part" $brd_part $obj
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# set_property "corecontainer.enable" "0" $obj
# set_property "ip_cache_permissions" "read write" $obj
# set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-hdmi-out/repo'.
# add_files -quiet $src_dir/hdl
# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -part $part -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
# } else {
#   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" $part $obj
# set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
# set_property "steps.synth_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.synth_design.args.fsm_extraction" "off" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -part $part -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2015" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" $part $obj
# set_property "steps.opt_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.place_design.args.directive" "RuntimeOptimized" $obj
# set_property "steps.route_design.args.directive" "RuntimeOptimized" $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:$proj_name"
INFO: Project created:hdmi-out
# set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
# if {[llength $bd_list] != 0} {
#   add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
#   open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
#   set design_name [get_bd_designs]
#   set file "$origin_dir/src/bd/$design_name/$design_name.bd"
#   set file [file normalize $file]
#   set file_obj [get_files -of_objects [get_filesets sources_1]

  1. ]
    #   if { ![get_property "is_locked" $file_obj] } {
    #     set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
    #   }
    #  
    #   # Generate the wrapper
    #   set design_name [get_bd_designs]
    #   add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
    #
    #   set obj [get_filesets sources_1]
    #   set_property "top" "${design_name}_wrapper" $obj
    # }
    Adding cell -- digilentinc.com:ip:axi_dynclk:1.0 - axi_dynclk_0
    Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
    Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_0
    Adding cell -- xilinx.com:ip:xlconstant:1.1 - xlconstant_1
    Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_btn
    Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_hdmi
    Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_led
    Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_sw
    Adding cell -- xilinx.com:ip:axi_vdma:6.2 - axi_vdma_0
    Adding cell -- xilinx.com:ip:axis_subset_converter:1.1 - axis_subset_converter_0
    Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
    Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1
    Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
    Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0
    Adding cell -- xilinx.com:ip:v_tc:6.1 - v_tc_0
    Adding cell -- digilentinc.com:ip:rgb2dvi:1.3 - rgb2dvi_0
    CRITICAL WARNING: [BD 41-51] Could not find bus definition for the interface: TMDS
    CRITICAL WARNING: [BD 41-49] Could not find abstraction definition for the interface: TMDS
    CRITICAL WARNING: [BD 41-49] Could not find abstraction definition for the interface: TMDS
    CRITICAL WARNING: [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:tmds_rtl:1.0
    CRITICAL WARNING: [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:tmds_rtl:1.0', cannot be found. Interface port: 'TMDS' cannot be created
    CRITICAL WARNING: [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:tmds_rtl:1.0
    CRITICAL WARNING: [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:tmds_rtl:1.0', cannot be found. Interface port: 'TMDS' cannot be created
    WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0/aRst_n(rst)
    Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
    Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Adding cell -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice
    Adding cell -- xilinx.com:ip:axi_data_fifo:2.1 - s00_data_fifo
    Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
    Successfully read diagram <hdmi_out> from BD file <../src/bd/hdmi_out/hdmi_out.bd>
    open_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 892.184 ; gain = 45.504
    ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'hdmi_out.bd' is locked. Locked reason(s):
    * BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
    List of locked IPs:
    hdmi_out_axi_dynclk_0_0
    hdmi_out_rgb2dvi_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

    while executing
"make_wrapper -files [get_files $design_name.bd] -top -force"
    invoked from within
"if {[llength $bd_list] != 0} {
  add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  open_bd_design [glob -nocompla..."
    (file "create_project.tcl" line 125)
set_property  ip_repo_paths  {c:/git/Zybo-hdmi-out/repo C:/git/digilent_vivado_lib/vivado-library} [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/Zybo-hdmi-out/repo'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/git/digilent_vivado_lib/vivado-library'.
report_ip_status -name ip_status
upgrade_ip -vlnv digilentinc.com:ip:rgb2dvi:1.4 [get_ips  hdmi_out_rgb2dvi_0_0] -log ip_upgrade.log
Upgrading 'C:/git/Zybo-hdmi-out/src/bd/hdmi_out/hdmi_out.bd'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'kClkRange' from '1' to '2' has been ignored for IP 'hdmi_out_rgb2dvi_0_0'
WARNING: [IP_Flow 19-3501] Upgraded hdmi_out_rgb2dvi_0_0 from RGB to DVI Video Encoder (Source) 1.3 to RGB to DVI Video Encoder (Source) 1.4, with warnings. Please review the message log.
WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0_upgraded_ipi/aRst_n(rst)
CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'IP hdmi_out_rgb2dvi_0_0' has identified issues that may require user intervention. Please review the upgrade log 'c:/git/Zybo-hdmi-out/proj/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
Wrote  : <C:/git/Zybo-hdmi-out/src/bd/hdmi_out/hdmi_out.bd>
Wrote  : <C:/git/Zybo-hdmi-out/src/bd/hdmi_out/ui/bd_f2526487.ui>
INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/git/Zybo-hdmi-out/proj/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips hdmi_out_rgb2dvi_0_0] -no_script -sync -force -quiet
report_ip_status -name ip_status
validate_bd_design
INFO: [xilinx.com:ip:axi_vdma:6.2-16] /axi_vdma_0
                    All clocks connected to AXI VDMA are not identical, therefore configuring AXI-VDMA in ASYNC mode.
validate_bd_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1073.465 ; gain = 0.000

 

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