Zybo DDR3-533 bandwidth

[Evocati]

Hi all,

    I asked a question about how to use DDR on Zybo previously here: https://forum.digilentinc.com/topic/1017-how-to-use-the-ddr-on-zybo/

    Now, I can successfully use AXI_DMA to write and read video data into and out from on-board DDR.

    But still I have doubt about the DDR3-533 bandwidth in the reference manual: http://www.xilinx.com/support/documentation/university/XUP Boards/XUPZYBO/documentation/ZYBO_RM_B_V6.pdf

    On page-12, it says the bandwidth = 1066Mbps. So that's around 125MB/s. But I can successfully read one frame and write one frame of 720p video data at the same time using Zybo.

    For that, the bandwidth is 1280 x 720 x 4 Bytes x 60Hz= 240MB/s for one read or one write channel. The sum of read and write combined is 240MB/s x 2 = 480MB/s. This is much larger than 125MB/s in the reference manual.

 

    But I do meet problem when reading 2 frames each time for my project on motion detection. The output video is purely noise. The bandwidth required for the motion detection is 1 write channel + 2 reads channel = 3 x 240MB/s = 720MB/s

       

    I am currently debugging my design and my first thought is that 720MB/s is beyond the max bandwidth for Zybo DDR.

    However, the number in reference manual does not seem to make sense to me since the bandwidth of 480MB/s works for Zybo DDR. And some online reference about DDR bandwidth(eg. http://frankdenneman.nl/2015/02/19/memory-deep-dive-memory-subsystem-bandwidth/) shows typical DDR3 has much large transfer rate. (DDR3-533 is not there, but I think it should be in the same magnitude of DDR3-800)

    Can we double check that the reference manual gives the right number for DDR3 bandwidth?

    This is probably the last step of my motion detection project. I hope I can finish it soon and post my project and some tips on the forum to help those who wanna do similar things. 

    Thank you,

Hao

    

 

[AndrewHolzer]

Hi Evocati,

The calculations you are performing don't account for the data width of the DDR3 on the ZYBO, which is x16. Further, the ZYBO carries two DDR3 memory components, which can double the bandwidth. So the final bandwidth looks more like 4000MB/s. Effective bandwidth might be less than this number and depends on the burst length. Because you are working with video your effective bandwidth shouldn't be much smaller than our estimate. Further, the required bandwidth you need for your project is easily achievable.

I suspect that your issue is coming from the HP interconnect between the PL and PS subsystems. You could try speeding up the clock on those interconnects, or you could use multiple interconnects. If you choose the later solution, I suggest that you use the HP0 and HP2 interfaces because you won't be sharing bandwidth between them.

Hope this helps you,

Andrew

[Evocati]

Thank you Andrew for the clear explanation!

I finally debugged it out last night. The reset signal for some blocks in PL was massed up. Now the system works fine.

 

Thanks,

Hao