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Initializing block memory contents for synthesis


I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado?

Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?


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".COE" files are only read when you generate the IP - if you edit the .COE and don't regenerate the IP block nothing will change - pretty silly!

If you search the web you will find examples of a function to read in data at synthesis time.... e.g. http://electronics.stackexchange.com/questions/180446/how-to-load-std-logic-vector-array-from-text-file-at-start-of-simulation . You should be able to modify that to read in multiple blocks of data into different addresses. 

Once you get this strategy working once, it is a far more friendly way to achieve what you are after than the Block Memory Generator, IMO, and integrates better with source control systems and build systems. http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst_v6s6.pdf will give you examples to follow that will correctly infer BRAM blocks, you will just need to add in the above function to initialize the contents.



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