Nexys3 VGA output

[ivan]

Hello everyone.

I'm currently trying to create simple VGA EDK project to show something on the LCD monitor with Nexys3 board.

Nexys3 board has Micron celular RAM and I have a problem that every row is represented by four same rows on the screen. I think that my problem is like problem described on Xilinx Community forum: https://forums.xilinx.com/t5/Embedded-Development-Tools/xps-tft-problem-VGA-displays-repeated-rows/m-p/164338/highlight/true#M19715

I've used PLB bus and tried setting Video Memory on base address of Micron RAM and on high addres - 2 MB. I have also tried to set Video Memory to whole Micron RAM (16 MB). Micron RAM was successfully tested with the SDK built in memory test.

For software code, I used example from Xilinx (xtftexample.c).

I think that problem is with speed of Micron RAM. I found that in asynchronus mode you need to wait 70 ns for data to be ready. This means that frequency of accessing to Micron RAM is about 14.29 MHz and TFT controller works with clock of 25 MHz.

Does anyone have example EDK project which uses Micron RAM in synchronous mode?

If you need any information about my project, please let me know.

I would appreciate any help.

[sbobrowicz]

If you want to give using existing cores a shot, your best bet would be to switch to ISE 14.7 and use the AXI_EMC core in either synchronous SRAM or PSRAM mode. I can say we played around with the memory controller IP cores a bit (both the one included in PLB designs and the axi_emc) and never got the synchronous mode working in Microblaze designs, but we very well could have missed something.

If the AXI_EMC core doesn't work then it will probably fall on you to write a custom memory controller that initiates the synchronous bursts and presents the data over the AXI interface in a way that allows the Microblaze system to do burst reads and writes. That's a pretty solid chunk of work, but would be a cool project.