DFS_OSCILLATOR_MODE Warning on Atlys

[ASMartin]

Hi.

I need some help about ISE Xillinx.

I used a combined DCM-CLKGEN (master) and a DCM_SP (slave) clock generators to obtain 75.25 MHZ for HD (720p) HDMI output at 60Hz. This is the code:

TMDS_MASTER_DCM: DCM_CLKGEN
generic map (
   CLKFXDV_DIVIDE  => 2,              -- CLKFXDV divide value (2, 4, 8, 16, 32)
   CLKFX_DIVIDE    => 100,            -- Divide value - D - (1-256)
   CLKFX_MULTIPLY  => 33,             -- Multiply value - M - (2-256)
   SPREAD_SPECTRUM => "NONE",         -- Spread Spectrum mode "NONE"
   STARTUP_WAIT    => FALSE,          -- Delay config DONE until DCM_CLKGEN LOCKED
   CLKIN_PERIOD    => 10.000,         -- Input clock period specified in ns
   CLKFX_MD_MAX    => 0.000           -- Maximum M/D ratio for timing anlysis
)
port map (
   -- Input clock
   CLKIN           => mclk,           -- Input clock (100MHz Master Clock)
   -- Output clocks
   CLKFX           => clkfx_master,   -- Generated clock output (33MHz)
   CLKFX180        => open,           -- Generated clock output 180º phase shift
   CLKFXDV         => open,           -- Divided clock output
   -- Ports for dynamic phase shift
   PROGCLK         => '0',            -- Clock input for M/D reconfiguration
   PROGEN          => '0',            -- Active HIGH program enable
   PROGDATA        => '0',            -- Serial data input for M/D reconfiguration
   PROGDONE        => open,           -- Successful re-programming (active HIGH)
   -- Other control and status signals
   FREEZEDCM       => '0',
   LOCKED          => lock_master,    -- Locked output
   STATUS          => open,           -- DCM_CLKGEN status
   RST             => reset           -- Reset input pin
);

TMDS_MASTER_BUFG : BUFG
port map (
   O => clkfx_master_buf,
   I => clkfx_master
);

----                         Slave DCM Configuration
----
----       Output       Output       Phase      Duty      Pk-to-Pk     Phase
----       Clock       Freq (MHz)  (degrees)  Cycle (%)  Jitter (ps)  Error (ps)
----    ------------------------------------------------------------------------
----     clkfx_slave     74.250      0.000      50.0        469.360     150.000
----
----
----       Input Clock       Freq (MHz)    Input Jitter (UI)
----    -----------------------------------------------------
----     clkfx_master_buf      33.000           0 .010

TMDS_SLAVE_DCM: DCM_SP
generic map (
   CLKDV_DIVIDE          => 2.000,                 -- CLKDV divide value
   CLKFX_DIVIDE          => 4,                     -- Divide value CLKFX outputs
   CLKFX_MULTIPLY        => 9,                     -- Multiply value CLKFX outputs
   CLKIN_DIVIDE_BY_2     => FALSE,                 -- CLKIN divide by two
--   CLKIN_PERIOD          => 30.303,                -- Input clock period (ns)
   CLKOUT_PHASE_SHIFT    => "NONE",                -- Output phase shift
   CLK_FEEDBACK          => "1x",                  -- Feedback source
   DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",  -- SYSTEM_SYNCHRNOUS
   DFS_FREQUENCY_MODE    => "LOW",                 -- Unsupported
   DLL_FREQUENCY_MODE    => "LOW",                 -- Unsupported
   DSS_MODE              => "NONE",                -- Unsupported
   DUTY_CYCLE_CORRECTION => TRUE,                  -- Unsupported
   FACTORY_JF            => X"c080",               -- Unsupported
   PHASE_SHIFT           => 0,                     -- Amount of fixed phase shift
   STARTUP_WAIT          => FALSE                  -- Delay config DONE til LOCKED
)
port map (
   -- Input clock
   CLKIN                 => clkfx_master_buf,   -- Clock input          
   CLKFB                 => '0',                -- Clock feedback input
   -- Output clocks
   CLK0                  => open,               -- 0 degree clock output
   CLK90                 => open,               -- 90 degree clock output
   CLK180                => open,               -- 180 degree clock output
   CLK270                => open,               -- 270 degree clock output
   CLK2X                 => open,               -- 2X clock frequency output
   CLK2X180              => open,               -- 2X clock frequency, 180 degree
   CLKFX                 => clkfx_slave,        -- Digital Frequency Synthesizer
   CLKFX180              => open,               -- 180 degree CLKFX output
   CLKDV                 => open,               -- Divided clock output
   -- Ports for dynamic phase shift    
   PSCLK                 => '0',                -- Phase shift clock input
   PSEN                  => '0',                -- Phase shift enable
   PSINCDEC              => '0',                -- Phase shift increment/decrement
   PSDONE                => open,               -- Phase shift done output
   -- Other control and status signals    
   LOCKED                => lock_slave,         -- DCM_SP Lock Output
   STATUS                => open,               -- DCM_SP status output
   RST                   => reset_slave,        -- Active high reset input
   -- Unused pin, tie low     
   DSSEN                 => '0'                 -- Specify to GND
);

TMDS_SLAVE_BUFG : BUFG
port map (
   O => clkfx_slave_buf,
   I => clkfx_slave
);

And I obtain the following message when mapping:

Timing:3159 - The DCM, Clocking/TMDS_MASTER_DCM, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained using FROM/TO constraints.

I would like to avoid this warning, but I can't find the trouble. Indeed DCM_CLKGEN does not define any attribute regarding DFS_OSCILLATOR_MODE.

Thanks in advance. 

[sbobrowicz]

My bet is that the DCM_CLKGEN primitive always configures the DCM this way, so whenever you use it you see this warning. It could be a useful reminder to those that try to cross clock domains between the input clock and one of the generated clocks... Either that or it's just a bug and they forgot to remove a warning that no longer is true since they deprecated the DFS_OSCILLATOR_MODE attribute. Either way I don't think there is anything you can do about it, except try to figure out how to use the DCM_SP primitive to instantiate both of the DCMs in your design.

These types of warnings are exactly the reason why Xilinx introduced the "Critical Warnings" into Vivado. Basically "Warnings" and then "Infos" only need to be referred to when trouble shooting a design that doesn't work, and "Critical Warnings" should always be addressed (like you would a warning from a C or C++ compiler). My latest ZYBO design has 0 Critical Warnings, 327 Warnings, and 2,383 infos.

[ASMartin]

Hi Sam, thanks a lot for your support and information.

I've to use DCM_CLKGEN because I need a 33/100 ratio and I can't obtain that clock ratio with a DCM_SP (out of range).

So I will suffer this warnings

[hamster]

I'll also look at your issue when I next get a chance...

 

Don't you  want to x 10 (to give a VCO freq of 1,000 MHz, then divide by 3 to give 33?

The input clock times the mult factor must be within a fixed range (600MHz to 1.5GHz from memory) - x33 won't work!

 

Mike

[ASMartin]

Hi Mike,

Thanks for your solution but range is now working,

CLKFX_DIVIDE in range (1 to 256)

CLKFX_MULTIPLY in range (2 to 256)

for DCM_CLKGEN, but for DCM_SP

CLKFX_DIVIDE in range (1 to 32)

CLKFX_MULTIPLY in range (2 to 32)

So it's not possible to synthesize 33Mhz I need to obtain 74.25 MHz.

The trouble is just the warning message.

[hamster]

Oh,yeh 33/100 != 1/3 - how silly!

Here's how I work through the rations like this:

100:74.25

400 : 297

2*2*2*2*5*5 : 3*3*3*11

(2*2*2*2)*(5*5) :  (3*3)*(3*11)

Try going  x9  / 25 first, to give 36MHz, with a VCO of 900MHz,

Then going x33 / 16, giving 74.25 with a VCO of 1,188MHz

[ASMartin]

Well, 33 is not allowed (greater than 32) but I will try these ratio converters: x11/16 to give 68.75 MHz (with a VCO working at 1100 MHz) and x27/25  to give 74.25 MHz (with an VOC working at 1856.25 MHz). Thanks for your help, mate. 

[hamster]

But did you get rid out your error?

[ASMartin]

No, still same error after implementation.

[mwagner]

It should also possible to do this in two steps from 25 * 27 / 25 = 27.000 MHz. 27 MHz is the fundamental osc freq for video.