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ARTY: Microblaze reference - Vivado 2015.2


mindcircus

Question

Hello,

I've been trying to implement the reference design described in wiki in Vivado 2015.2, but I get a timing violation in implementation. I follow the instructions step by step and I've even tried to change the implementation strategy to Explore, without any effects. As far as I can see the only difference is that in wiki the implementation was done in Vivado 2015.1. Has anybody else faced this problem?

Thank you in advance!

 

PS. I attach a screenshot of the timing summary in case it helps...

ARTY_TimingSummary.PNG

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Hey all,

I just checked the board file and it looks fine, it uses the xc7a35ticsg324-1L part. Are you using the version obtained from here: https://reference.digilentinc.com/vivado:boardfiles2015 ? Also, your screenshot seems to suggest your design is targeting the correct part.

As for the timing error, it is reporting that you attached your 166.667 MHz clock to the clk_ref_i signal of the MIG, which is incorrect. As it turns out, this is not your fault: though the picture in the guide is correct, the text in the guide tells you to connect the incorrect clocks to both the clk_ref_i and sys_clk_i pins. Make sure that you connect the 200MHz clock (clk_out3) to clk_ref_i and the 166.667MHz (clk_out2) clock to sys_clk_i.

I just fixed this in the guide, thanks for (inadvertently) pointing this out :)

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Thanks for the help JColvin!

One more thing... It seems that the board files are written for a different FPGA device (xc7aticsg324-1L instead of xc7a35tcsg324-1). I can't correct them right now, but I've manually rebuilt the design for the correct device and the problem persists. I think it would be a good idea to provide an updated version of the xmls and MIG's project if there is not any other reason to keep them this way...

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Hello Mindcircus,

It is bothersome that the design has timing issues and the board file isn't appearing to target the correct FPGA.  Realistically, the timing error may not even affect the design.  Unfortunately it looks like it is associated with the memory so it might be a little unstable.  The fact that it builds makes me think the displayed FPGA is not what it is building for but I am not sure.

Do you have any errors? besides the timing errors?  If not, then it might run fine.

Hopefully we can get the board file fixed and find a solution that allows for the design to build without a timing error.

Best of luck,

Marshall

 

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I just tried the design in the Wiki with Vivado 2015.4 and it generates a bitstream without timing errors. However, the MIG 7 block auto instantiates the XADC with temp bus necessary to maintain timing. If I instantiate an axi-lite xadc wizard with temp bus and connect it to the MIG 7 I get timing path failures on the temp bus between XADC and MIG although it claims the bitstream generation was good but there is an implementation critical warning. I looked at Xilinx web site and there is a document that states the XADC needs to be in DRP mode with Dclk enabled. If I configure this way, the temp bus is removed which causes errors. The only way to get a temp bus is to use the axi-lite interface for the XADC wizard.

I tried this with 2015.2 and got the same results

Any advice would be welcome?

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I dug into this issue and I found that the Temp_Bus[11:0] is an asynchronous bus that is sampled every 10uSec in the MIG 7. After looking at the Verilog for the MIG 7 Temperature monitor I found that the Temp_Bus is passed through 5 Async Registers. Based on this I created a constraints file (temp_bus.xdc) with the following constraint:


set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[11]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[11]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[10]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[10]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[9]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[9]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[8]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[8]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[7]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[6]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[6]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[5]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[4]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[3]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[3]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[2]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[2]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[1]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[1]/D}]
set_false_path -setup -from [get_pins {system_i/xadc_wiz_0/inst/AXI_XADC_CORE_I/temperature_update_inst/temp_out_reg[0]/C}] -to [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D}]

The design now has no timing errors.

 

 

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