nexys4 Nexys 4 DDR sram-to-ddr map problem

[BlazeMicro]

Hello,
I am using Xilinx ISE 14.7

I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram
I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end.

I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons.

 

I started Translate and Map, Translate returned a lot of messages like:
 

WARNING:ConstraintSystem:119 - Constraint <NET "sw<0>"          LOC=J15 |>
   [Nexys4DDR_Master.ucf(13)]: This constraint cannot be distributed from the
   design objects matching 'NET "sw<0>"' because those design objects do not
   contain or drive any instances of the correct type.

And Map returned:
 

ERROR:MapLib:979 - LUT6 symbol "Mmux_ram_addr[26]_ram_addr[26]_mux_10_OUT_B11"
   (output signal=Mmux_ram_addr[26]_ram_addr[26]_mux_10_OUT_B1) has input signal
   "btnr" which will be trimmed. See Section 5 of the Map Report File for
   details about why the input signal will become undriven.

 

I found there http://www.xilinx.com/support/answers/34900.html a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same).

It removed these errors but now Map returned different error:
 

ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the
   I/O bank 34.
   They require a voltage reference supply from the VREF pin(s) within the same
   I/O bank to be available.
   The following VREF pins are currently locked and can't be used to supply the
   necessary reference
   IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
   List of locked IOB's:
       ddr2_dq<2>
       ddr2_dq<1>
       ddr2_dq<4>
       ddr2_dq<3>
       ddr2_dq<15>
       ddr2_dq<0>
       ddr2_dq<9>
       ddr2_dq<6>
       ddr2_dq<5>
       ddr2_dq<8>
       ddr2_dq<7>
       ddr2_dq<10>
       ddr2_dq<11>
       ddr2_dq<12>
       ddr2_dq<13>
       ddr2_dq<14>

 

I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem.
The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications.

Could someone help me with this issue?

 

[JColvin]

Hi BlazeMicro,

I have asked some of our Applications Engineers about this; they'll get back to you here on the forum.

Thanks,
JColvin

[BlazeMicro]

Hi JColvin,

Thank you for fast response.

What I also want to add is that my project is a simple demo. I have one Verilog file which if you press one of the buttons increments or decrements ddr address and it puts there a value which is encoded on switches. I also use leds. I do not use instances of IP cores, XADC or something like that. The only thing that i use is instance of Mixed-mode clock manager (MMCM) for generating 200MHz clock.

Thanks,

BlazeMIcro

[sLowe]

Hey BlazeMicro,

You should not have to put the ddr pinouts in your master UCF if you are using the MIG. You should use the MIG project files to configure the mig and the ram2ddr component will instantiate it within itself, 

-Sam

 

 

[BlazeMicro]

Thank you sLove for your answer.

I want to use ram2ddrxadc.ngc file which is in ddr-to-sram pack. I think, that if i want to use netlist i do not need to use MIG project because all MIG generated stuff is packed into netlist file of the ddr-to-sram component (I hope so).

In my main module i did something like:
 

module main
	(
		/* OTHER MODULE SIGNALS ABOVE*/
		input [12:0] ddr2_addr,  
		input ddr2_ba,     
		input ddr2_ras_n,   
		input ddr2_cas_n,   
		input ddr2_we_n,    
		input ddr2_ck_p,    
		input ddr2_ck_n,    
		input ddr2_cke,     
		input ddr2_cs_n,    
		input ddr2_dm,      
		input ddr2_odt,     
		inout [15:0] ddr2_dq,      
		inout [1:0] ddr2_dqs_p,   
		inout [1:0] ddr2_dqs_n   
	);

 

And in the same module i've created an instance of ram2ddrxadc component. 

	reg [26:0] ram_a;
	reg [16:0] ram_dq_i;
	wire [15:0] ram_dq_o;
	reg ram_cen;
	reg ram_oen;
	reg ram_wen;
	reg ram_ub;
	reg ram_lb;

	ram2ddrxadc ram
	(
		 clk_200MHz_i(clk),
		 rst_i(reset),
		 device_temp_i({12{1'b0}}),
		 ram_a(ram_a),     
		 ram_dq_i(ram_dq_i),     
		 ram_dq_o(ram_dq_o),     
		 ram_cen(ram_cen),      
		 ram_oen(ram_oen),      
		 ram_wen(ram_wen),      
		 ram_ub(ram_ub),       
		 ram_lb(ram_lb),       
		 ddr2_addr(ddr2_addr),  
		 ddr2_ba(ddr2_ba),     
		 ddr2_ras_n(ddr2_ras_n),   
		 ddr2_cas_n(ddr2_cas_n),   
		 ddr2_we_n(ddr2_we_n),    
		 ddr2_ck_p(ddr2_ck_p),    
		 ddr2_ck_n(ddr2_ck_n),    
		 ddr2_cke(ddr2_cke),     
		 ddr2_cs_n(ddr2_cs_n),    
		 ddr2_dm(ddr2_dm),      
		 ddr2_odt(ddr2_odt),     
		 ddr2_dq(ddr2_dq),      
		 ddr2_dqs_p(ddr2_dqs_p),   
		 ddr2_dqs_n(ddr2_dqs_n)   
	 );

 

And after Synthesis everything is OK.

Then i added .ucf file with DDR2 pinout to the project to let ISE know how to map it.
I added this pinout as a additional .ucf file (so i had Nexys4DDR_Master.ucf and Nexys4DDRmemorypinout.ucf in one project) and i also tried to copy the content of Nexys4DDRmemorypinout.ucf to Nexys4DDR_Master.ucf and use it as one file. Both approaches crashed.

I also tried to use ISE project which is located in Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp and it has files created by MIG so it should run without any problems but it failed in Map stage with error that i mentioned earlier.

There: https://reference.digilentinc.com/nexys4-ddr:sram are two download links: one with netlist/source and one with ucf with ddr pinout. I thought that i should use both to create design with ddr2.

If i am wrong please tell me how should i use ram2ddr_refcomp.zip (source or netlist) and nexys4ddrmemorypinout.zip

[sLowe]

Oh in that case, try deleting your MIG.ucf file since the .ngc should constrain the ddr pinouts. The .UCF is useful when you go through the MIG yourself and have to specify the ports used. I personally have never  used the .ngc file so I dont know this for sure. I in the past have just gone through the wizard.

 

[BlazeMicro]

I removed Nexys4DDRmemorypinout.ucf and now i have:
 

ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<2>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<1>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<4>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<3>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<15>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<0>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<9>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<6>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<5>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<8>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<7>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<10>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<11>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<12>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<13>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<14>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:Pack:1642 - Errors in physical DRC.

 

I've uploaded my project here if someone wants to see it:
http://www.speedyshare.com/4BR7m/ddr2-fpga.zip

I've also tried to use Source of ddr-to-sram and MIG wizard and the problem was the same:
 

ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the
   I/O bank 34.
   They require a voltage reference supply from the VREF pin(s) within the same
   I/O bank to be available.

(...)

 

I saw other threads abut DDR like:
https://forum.digilentinc.com/topic/823-instantiating-nexys4-sram-to-ddr-component/

And it seems that other users of this board started ddr-to-sram component.

I also did exactly the same as tom21091 has written in this thread and it still does not work, the same errors

(with Nexys4DDRmemorypinout.ucf i have ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the
   I/O bank 34. and without it i have ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<2>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.)

[AndrewHolzer]

Hi BlazeMicro,

As you've noted other users have been having issues with the MIG in ISE. This seems to stem from creating the IP from the project manager instead of the standalone core generator. There is a workaround detailed in this post that requires you copy and rename the UCF and include it in the project manually.

I hope the linked post helps you sort these issues out further.
Andrew