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Nexys4 Ethernet Example


AlistairCheeseman

Question

The reference manual for the nexys4 states ‘An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys4 product page at www.digilentinc.com.’.

I have looked at the project page and have managed to find the UART/MIC/GPIO and factory examples but I cannot find any reference to the ethernet examples. http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4

I have also tried searching on the website for any ethernet example(s) and could not find any. If anyone could point me to the ethernet example for the nexys4 I would very appreciative, if not any material would be very helpful.

I have found this post on this forum, but could not find anything specific to the nexys 4 board.

Thanks in advance

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Hi Paul,

Sorry for the late response. I have enlarged some of the screen shots to assist with following the getting started with microblaze servers tutorial for the Nexys 4. I went through the nexys 4 getting started with microblaze servers using Vivado 2016.2 and made the attached project following the tutorial. I haven't had a chance to verifiy it yet but I will. If you are using the nexys 4 ddr let me know and i can get that for you. Hope this helps.

cheers,

Jon

Nexys4_GSMS.zip

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I am not sure if this is of any help but I have the project files for the microblaze example implementing the echo server for vivado 2015.2. You may just be able to upgrade the project to the latest version & (hopefully) it should work  https://github.com/AlistairCheeseman/WindTunnelApparatus/tree/master/Firmware/Tests/FPGA/FPGAEchoExample

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Hi,

Do Digilent offer any reference design for ethernet related example or a completed project of the above Ethernet - Microblaze server wiki ? 

 

Some figures (which shows the parameters used in the design, eg: section 3.2 of wiki) are not very clear. Also, connections made by the tool after running Run Block Automation and Run Connection Automation  are slightly different from my design either due to a different version of Vivado or due to some other reason. 

A reference design would be a very helpful in this case. 

Thanks,

Paul

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Hi, I triple checked. All steps as in the tutorial, including Block automation for MIG IP before running Run Connection Automation. And still , the microblaze_0 checkbox is not there for me to uncheck, and after connection automation , the  axi_mem_intercom block is missing.

A side note, in order to get the microblaze_0_xlconcat & microblaze_0_axi_intc blocks you need to enable interrupts for the Microblaze (as obvious as it seems , it is ot stated in the tutorial).

Is there any guru from digilent (maybe the author of the tutorial) available to help?

 

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Hi there DigitalDev,

What are you looking for? If you are okay with a Microblaze implementation, we have a guide that steps you through the implementation of an echo server over ethernet on the Nexys 4. Once you've set the design up, you can add more functionality.

Let me know if this is what you are looking, and if there is anything else I can help with.
Andrew

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Hi Justin,

Is this happening after you Run Connection Automation? When you run the tool, you have the option of explicitly defining the clock source for a peripheral clock connection, or letting the tools decide. I would warrant that you are letting the tools automatically make a connection, and they are deciding to connect the mii-rmii converter to sys_clock. Re-run Connection Automation, but click on ref_clk underneath the mii-to-rmii selection and choose /clk_wiz_1/clk_out2 for the Clock Connection, and see if that solves your problem.

Let me know if this works out for you (or if it doesn't),
Andrew

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I am having difficulties using Vivado 2015.4 for the above echo server. It appears that a piece of IP called mig_7series_0 is being created in your example but that may be because I assume some picture may be recycled from the Nexys4 DDR page. My error seems to be that when i follow the steps exactly clk_out2 is not wired to the rmii-mii converted but instead sys_clock is getting connected. Any ideas why this may be happening and how I can fix it?

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Thanks for detailed instruction on getting it work.

It worked for me after I followed the instructions but Xilinx Vivado reports that timing constraints are not met.
Do you guys also get timing violations?
What can be done to resolve timing issues?

Thank you,
Alexander.

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