Arty Block Design reset

[Michael Harpe]

I am working with the Block Design flow in Vivado 2015.3.

I don't seem to be getting how to connect the reset system. My design keeps acting like the clock is being held in reset. When I look closely it appears that the reset signal on the Arty is active low while the reset module in the design expects active high.

What am I missing here?

Michael Harpe

[JColvin]

Hi Michael,

I have asked our Applications team about this; they will get back to you here on the forum.

Thanks,
JColvin

[Michael Harpe]

Thanks. Also, getting the design to implement was interesting. I have quite a time getting the property CFGVBS set properly. I finally found the right screen to set it and it ended up in my constraints file at the bottom. I already had it at the top so I learned that order counts :-).

I freely admit that I am new to the FPGA world and Vivado. Thanks for passing on my request.

[jpeyron]

Hi michael,

Could you post project so we can see the errors. 

thank you,

Jon

[Michael Harpe]

Which files do you want? I tried to upload the project archive but this site complained that it was too large.

[sLowe]

Hey Michael,

I don't know why Vivado is doing this. In the meantime you can open up the clocking wizard, click on the output clock tab, and set reset polarity to be active low.

The board file seems to define the reset pin as active low but I will keep investigating. 

Hope this helps,

- Sam