• 0
Michael Harpe

Arty Block Design reset

Question

I am working with the Block Design flow in Vivado 2015.3.

I don't seem to be getting how to connect the reset system. My design keeps acting like the clock is being held in reset. When I look closely it appears that the reset signal on the Arty is active low while the reset module in the design expects active high.

What am I missing here?

Michael Harpe

Edited by JColvin

Share this post


Link to post
Share on other sites

5 answers to this question

Recommended Posts

  • 0

Thanks. Also, getting the design to implement was interesting. I have quite a time getting the property CFGVBS set properly. I finally found the right screen to set it and it ended up in my constraints file at the bottom. I already had it at the top so I learned that order counts :-).

I freely admit that I am new to the FPGA world and Vivado. Thanks for passing on my request.

Share this post


Link to post
Share on other sites
  • 0

Hey Michael,

I don't know why Vivado is doing this. In the meantime you can open up the clocking wizard, click on the output clock tab, and set reset polarity to be active low.

The board file seems to define the reset pin as active low but I will keep investigating. 

Hope this helps,

- Sam

 

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now