Fractals on Genesys2.


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I've got my 1080i real-time fractal design running on the Genesys2 board, and the source checked in at https://github.com/hamsternz/FPGA_Mandelbrot - I spent last night getting rid of the 8-bit colour look, using the HDMI's 24 bit range.It uses about 100k flip-flops, 150k LUTs and 640 DSP slices, so uses a large chunk of the FPGA.

If anybody is after a reference point, the Kintex-7 FPGA on the Genesys2 added 0.670ns slack to the 225MHz design that just meets timing on he Artix-7. But I can't make can't make use of the extra speed as the calculations run at a multiple of the pixel clock.

The logic was also fast enough that I could implement 20% of the multipliers using LUTs - allowing me to get to 255 iterations in real time. 

 

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