Verilog - Data Type

[jotran00]

Hello,

Have you seen anywhere and experienced the data types below in Verilog?.

•      input wire;
•     output wire;

Per my understanding, both input and output data types themselves are wire already. Please correct me if I am wrong.

 

Thanks,

Jonathan Tran

     

 

[Commanderfranz]

Hi Jonathan,

You are correct, input and output types by default are wires. Only if you use the keyword reg with they change to a register type. Saying output wire isn't wrong, but is redundant. 

Hope this clears things up!

Kaitlyn

[jotran00]

Hi Kaitlyn,

 

Thanks you for clarifications.

Thanks

Jonathan Tran

 

[Alex]

Hi, FYI, A book "Verilog HDL 2nd Edition" written by Samir Palintkar can be a good reference. The first four chapters explain data types, modules and ports in Verilog. Then, you can have more understanding about the net, register, input and output in Verilog.