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Zybo LVDS input to the High-Speed PMOD?


Hi all,

I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW.
The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes.

Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras.
I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination?

The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are length matched. Are they? If not, what is the length difference so I can compensate on my side.
Sure, 340 MBit/s is low, but I like to have everything correct when working with LVDS.

Thanks for your time!
Best regards, Emil

Edited by JColvin
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Ok, here's the info I got:

First off, the signals on the ZYBO have a 40 Ohm characteristic impedance, which means they have an 80 Ohm impedance when used as differential inputs.

Here are the trace lengths for the differential pmod pairs. Note that the right most column is the addition of the distance between the connector and the 0Ohm Shunt and the distance between the 0Ohm shunt and the FPGA Package:

  Resistor to FPGA Package (mm) Connector to Resistor (mm) Connector to FPGA Package (mm)
JB1_N 62.5472 11.051 73.5982
JB1_P 63.2772 10.5732 73.8504
JB2_N 58.6251 10.3026 68.9277
JB2_P 59.4887 11.7819 71.2706
JB3_N 46.6437 24.5194 71.1631
JB3_P 46.2212 24.991 71.2122
JB4_N 56.5479 17.6469 74.1948
JB4_P 56.9383 17.5207 74.459
JC1_N 42.1211 15.6605 57.7816
JC1_P 42.1821 15.9288 58.1109
JC2_N 33.0162 12.6902 45.7064
JC2_P 33.9233 13.9195 47.8428
JC3_N 37.1697 14.7288 51.8985
JC3_P 38.677 14.6267 53.3037
JC4_N 37.7095 17.2073 54.9168
JC4_P 38.2814 15.555 53.8364
JD1_N 48.9606 10.0125 58.9731
JD1_P 49.1133 7.4855 56.5988
JD2_N 47.1184 15.8404 62.9588
JD2_P 47.2909 14.5663 61.8572
JD3_N 68.2658 9.9712 78.237
JD3_P 67.4153 9.5412 76.9565
JD4_N 77.1782 16.4407 93.6189
JD4_P 76.4804 15.389 91.8694

Note that the FPGA package also introduces a small delay between the package and the die. This delay is about 25ps-180ps depending on the pin. If you need to account for this as well, you will need to use the information in the .pkg file I've attached, which lists out the exact delay for each pin. I generated it with partgen -v in ISE 14.7. 

Keep us posted on your project. I want to know how fast you can push the pmod connectors!


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Xilinx has told me that you can use LVDS inputs when the bank is powered to 3.3V (outputs, however, are not allowed). I think this might require lying to the tools though. If your project throws a fit about voltage mismatches when you declare the pmod inputs as LVDS_25, try setting any other single-ended pins you are using on that bank to be LVCMOS25. 

As for the PCB design, I know that the pins are routed as proper differential pairs, but I don't know off the top of my head if the pairs are length matched. I'll ask our layout guy and get back to you.

Last thing I'll note, 340 Mbits/sec may be more than the Pmod connectors/ZYBO PCB can handle reliably. Worth a shot, but I've never run them that fast.

EDIT: I think you actually need to use the LVDS_25 IOSTANDARD, not LVDS. Changed above

Edited by sbobrowicz
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Thank you! Then I know where to start :)

 I am not overly worried about the PMOD itself, I have tried 1.5 GBit/s over a standard 0.1" header and that worked like a charm (though I do not know how good the eye was, but no but errors). Please come back with the length of each pair, it will help me greatly!

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Thanks for the info!
The 80 Ohms are a little difficult, I will have to add some impedance matching resistors but no problem.
The camera has 115 Ohm out (due to a design decision) so two 18 Ohm resistors will be enough to get close to matched impedance.

I will post some results as soon as I have them! 

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