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Zybo LVDS input to the High-Speed PMOD?

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Hi all,

I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW.
The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes.

Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras.
I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination?

The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are length matched. Are they? If not, what is the length difference so I can compensate on my side.
Sure, 340 MBit/s is low, but I like to have everything correct when working with LVDS.

Thanks for your time!
Best regards, Emil

Edited by JColvin
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Ok, here's the info I got:

First off, the signals on the ZYBO have a 40 Ohm characteristic impedance, which means they have an 80 Ohm impedance when used as differential inputs.

Here are the trace lengths for the differential pmod pairs. Note that the right most column is the addition of the distance between the connector and the 0Ohm Shunt and the distance between the 0Ohm shunt and the FPGA Package:

 Resistor to FPGA Package (mm)Connector to Resistor (mm)Connector to FPGA Package (mm)
JB1_N62.547211.05173.5982
JB1_P63.277210.573273.8504
JB2_N58.625110.302668.9277
JB2_P59.488711.781971.2706
JB3_N46.643724.519471.1631
JB3_P46.221224.99171.2122
JB4_N56.547917.646974.1948
JB4_P56.938317.520774.459
    
JC1_N42.121115.660557.7816
JC1_P42.182115.928858.1109
JC2_N33.016212.690245.7064
JC2_P33.923313.919547.8428
JC3_N37.169714.728851.8985
JC3_P38.67714.626753.3037
JC4_N37.709517.207354.9168
JC4_P38.281415.55553.8364
    
JD1_N48.960610.012558.9731
JD1_P49.11337.485556.5988
JD2_N47.118415.840462.9588
JD2_P47.290914.566361.8572
JD3_N68.26589.971278.237
JD3_P67.41539.541276.9565
JD4_N77.178216.440793.6189
JD4_P76.480415.38991.8694

Note that the FPGA package also introduces a small delay between the package and the die. This delay is about 25ps-180ps depending on the pin. If you need to account for this as well, you will need to use the information in the .pkg file I've attached, which lists out the exact delay for each pin. I generated it with partgen -v in ISE 14.7. 

Keep us posted on your project. I want to know how fast you can push the pmod connectors!

xc7z010clg400.pkg

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Xilinx has told me that you can use LVDS inputs when the bank is powered to 3.3V (outputs, however, are not allowed). I think this might require lying to the tools though. If your project throws a fit about voltage mismatches when you declare the pmod inputs as LVDS_25, try setting any other single-ended pins you are using on that bank to be LVCMOS25. 

As for the PCB design, I know that the pins are routed as proper differential pairs, but I don't know off the top of my head if the pairs are length matched. I'll ask our layout guy and get back to you.

Last thing I'll note, 340 Mbits/sec may be more than the Pmod connectors/ZYBO PCB can handle reliably. Worth a shot, but I've never run them that fast.

EDIT: I think you actually need to use the LVDS_25 IOSTANDARD, not LVDS. Changed above

Edited by sbobrowicz

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Thank you! Then I know where to start :)

 I am not overly worried about the PMOD itself, I have tried 1.5 GBit/s over a standard 0.1" header and that worked like a charm (though I do not know how good the eye was, but no but errors). Please come back with the length of each pair, it will help me greatly!

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Thanks for the info!
The 80 Ohms are a little difficult, I will have to add some impedance matching resistors but no problem.
The camera has 115 Ohm out (due to a design decision) so two 18 Ohm resistors will be enough to get close to matched impedance.

I will post some results as soon as I have them! 

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