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Yann Sionneau

Arty schematics missing FT2232 component

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Hi,

The Arty schematics are missing the FT2232 component, therefore we cannot see to which FPGA pins it is connected.

The only pins we know are UART_TX and UART_RX.

But what about other FTDI pins? Like the ones to control the FIFO mode of the FTDI chip.

Thanks!

Regards,

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Hey Yann,

The schematic for that component is proprietary, so that page is left blank in the board schematics. I can see from the product page that a final reference manual is not currently available there, however information can be found on the wiki page here. According to the information I have found, from the user side you only need access to TX and RX for serial communication, as there are virtual COM port drivers that handle all of the other functionality of the FTDI chip. The drivers and installation instructions can be found at FTDI's site here. Let me know if this answers your question or if you need any further information. 

Regards,

Nate

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On 10/8/2015 at 10:41 AM, NAEastland said:

Hey Yann,

The schematic for that component is proprietary, so that page is left blank in the board schematics. I can see from the product page that a final reference manual is not currently available there, however information can be found on the wiki page here. According to the information I have found, from the user side you only need access to TX and RX for serial communication, as there are virtual COM port drivers that handle all of the other functionality of the FTDI chip. The drivers and installation instructions can be found at FTDI's site here. Let me know if this answers your question or if you need any further information. 

Regards,

Nate

I have the Arty board and have been using it for the initial development of an Artix based project. I would like to utilize the FTDI FT2232H for JTAG (in Vivado) and USB serial communication.

From the Digilent forums I know that the FT2232 page has been omitted from the Arty schematic because it contains proprietary information. However the Arty user guide Wiki shows the connections.

Does the Wiki page contain the complete schematic or are there additional connections that are required? Does an attached EEPROM require specific data to be recognized by Vivado? 

Trust me, I do not plan to use this information for anything other than the development of our next generation of audio products. I will sign an NDA if necessary.

Regards,

Bob

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Hi Bob,

I personally don't know the answer to your question, but I have asked some of our applications engineers about it they will get back to you here on the forum.

Thanks,
JColvin

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Hi Bob,

Unfortunately, we would not be able to assist you with your questions about the EEPROM or the FT2232 because this part of the design is proprietary information.

Thank you,

Jon 

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On 2/18/2016 at 0:38 AM, bbauman said:
On 2/18/2016 at 0:38 AM, bbauman said:

I have the Arty board and have been using it for the initial development of an Artix based project. I would like to utilize the FTDI FT2232H for JTAG (in Vivado) and USB serial communication.

From the Digilent forums I know that the FT2232 page has been omitted from the Arty schematic because it contains proprietary information. However the Arty user guide Wiki shows the connections.

 

 

There is no problem to use the 2nd channel of the FT2232 on Arty, Basys3 and Nexys4 boards. All you need to know is to which FPGA pins the RXD and TXD and in case of nexys4 the RTS and CTS lines of the FT2232 are connected. This is documented in the master xdc and in the reference manual.

Than simply use it as USB-UART via /dev/ttyUSBx. With proper settings that works very well.

I'm using this in many designs on all three boards. With baud rates of 10 and 12 MBaud and throughputs of up to 1 MByte per second.

A bit of a nuisance is that only the Nexys4 has RTS/CTS connected so that hardware handshake can be used. On Basys3 and Arty I've to use XON/XOFF flow control and thus to ensure with proper escaping that these characters can be transmitted over this channel. Using flow control is a must at the speeds I use.

Bottom line: the USB UART part of the FT2232 can be used a medium speed data interface.
And a remark to Digillent: please connect RTS/CTS in future boards (as done on Nexys4).

 

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On February 26, 2016 at 4:33 AM, wfjmueller said:

There is no problem to use the 2nd channel of the FT2232 on Arty, Basys3 and Nexys4 boards. All you need to know is to which FPGA pins the RXD and TXD and in case of nexys4 the RTS and CTS lines of the FT2232 are connected. This is documented in the master xdc and in the reference manual.

Than simply use it as USB-UART via /dev/ttyUSBx. With proper settings that works very well.

I'm using this in many designs on all three boards. With baud rates of 10 and 12 MBaud and throughputs of up to 1 MByte per second.

wfjmueller, would you (or anyone else) be willing and able to post or link to some code (VHDL ideally but I'll take what I can get) that shows USB communication via the FT2232? I'm trying to get this working but I'm having trouble finding a point of entry. Thanks in advance. -dfergenson

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I'm using the Basys3 board and communicating with my PC at 4MBaud.  Communicating over the USB is done via the UART protocol.  Hence, to talk to the FT2232 you mention, you simply use the two wires of a UART.  This shows up inside my Linux box as /dev/ttyUSBx and acts ... just like a UART on both ends.

If you are looking for UART RTL code, you can find the UART code I'm using for my Basys3 copied into my S6SoC project here.  (It's in the trunk/rtl directory, in the rxuart.v and txuart.v files).  Cranked up, I've ran this UART from my Basys3 board to/from my host PC at 4MBaud while clocking the design at 100MHz.  (Sorry, I don't have my Basys3 project posted anywhere ...)

Dan

Edited by D@n
Oops! I was clocking my Basys3 design at 100 MHz, not 10MHz. Sorry.

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5 minutes ago, D@n said:

I'm using the Basys3 board and communicating with my PC at 4MBaud.  Communicating over the USB is done via the UART protocol.  Hence, to talk to the FT2232 you mention, you simply use the two wires of a UART.  This shows up inside my Linux box as /dev/ttyUSBx and acts ... just like a UART on both ends.

If you are looking for UART RTL code, you can find the UART code I'm using for my Basys3 copied into my S6SoC project here.  (It's in the trunk/rtl directory, in the rxuart.v and txuart.v files).  Cranked up, I've ran this UART from my Basys3 board to/from my host PC at 4MBaud while clocking the design at 10MHz.  (Sorry, I don't have my Basys3 project posted anywhere ...)

Dan

Thanks, Dan. I may look to the community for more help but when I do have a simple PC host application communicating with a simple VHDL program on a Basys3 I'll post it or a link to it here (unless someone beats me to it). -dfergenson

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Hi, I'm new to the Arty7 board and the Artix 7, but have used FTDI 2232H's with several other FPGA boards in the past. It's quite a common part, and quite capable.  I can't imagine what could possibly be proprietary about wiring up this part, as FTDI and every other board vendor out there provides complete schematics for their boards with this part.

So, two questions:

1. Are you (Digilent) serious about this being a proprietary area of your board?  I respectfully request you reconsider this in light of industry practice here.  Some users like or need to dig into details to make the most of the eval boards.  We almost didn't purchase or recommend these boards to our customer due to this omission.  It makes it look like the documentation is incomplete/out of date/unreliable.

2. The FT2232H is a very capable part. The way it's wired on the Arty7 is quite disappointing, as we are unable to use the MPSEE or byte-wide synchronous FIFO modes.  This wiring severely limits the data rates and features.  Are you planning a future version with the rest of the FT2232H data pins wired to the FPGA?  Other vendors do this with series resistor footprints; you can leave them unpopulated.  (We'll use an external USB board when higher speeds are needed.)

Thanks

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Hello,

1. The design with this specific part is not public. The decision to leave this page empty was taken fully by FTDI as we released the schematics for our boards and our designs.You can see that some of our boards have the design fully published (see Chipkit boards). I'm sorry but we cannot help you with that part of the design. 

2. The connection of the devices are made as specified in the project and can vary from one board to another depending on the specifications required for that board. Arty was designed specifically like this. Future boards might be different or not.

Best regards,

Bianca

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Okay, thank you for the background.  (Seems odd, but okay. Usually these boards are reference designs, as well, so the vendors would share the usage info.)

A related question to the FT2232C on the Arty board:

It appears that when I connect to ("open") the USB Serial Converter B port as a COM port from my PC that a reset is triggered at the FPGA, similar to clicking the red reset  button, e.g. CK_RST on the schematics.

Is this expected, and is there some way to disable that behavior?  Since I can't see the wiring of the part it's a mystery...

Thanks,

Scott

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It wouldn't be hard to reverse engineer the connections for the FT2232 on the board if you really wanted to. All you have to do is trace the connections from the FT2232 pins to determine what they're connected to and draw your own schematic. 

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Found it: From the Arty Reference web page there is a note about JP2 connecting the FT2232 BDBUS4 pin to the CK_RST line.  BDBUS4 is controlled by the "B" port on the FT2232.  When closing then reopening the COM/UART port this line toggles (drops low rapidly and slowly rises in about 3ms). In UART mode this pin is DTRn (data terminal ready bar), and it must be updated when the port is reopened. 

By disconnecting JP2 we break this connection to the FPGA and the reset from the FT2232 no longer causes the reset.

@JerryG - "It wouldn't be hard to reverse engineer the connections ..." That' s highly doubtful on a multi-layer board with a BGA package for the FPGA, with not all package pins brought out to headers. Or do you have some method to probe BGA pins on inner layers?

 

 

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21 hours ago, InPhaseDesign said:

@JerryG - "It wouldn't be hard to reverse engineer the connections ..." That' s highly doubtful on a multi-layer board with a BGA package for the FPGA, with not all package pins brought out to headers. Or do you have some method to probe BGA pins on inner layers?

You'd have to sacrifice a board and remove all of the components. Blind and buried vias would be the next challenge, but not too difficult with a sacrificial board. The effort you put into it depends on how desperately you need to know the connections. Not publishing the full schematic is just a form of security by obscurity and will only hide the information from the unmotivated. People reverse engineer ICs all the time--that's much harder than reverse engineering a PCB.

 

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@JerryG - Agreed, but that's way beyond reasonable effort for what should be a reference design (or for our project requirements). One would think the vendors would want designers to know how to user their parts... and if the board is doing something odd, they should at least help enlighten us. (I would note the far more complex AC701 board from Xilinx has complete schematics available, although it uses a different JTAG approach.)  By the way, for this it's possible a board x-ray would be easier...

Edited by InPhaseDesign

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1 hour ago, InPhaseDesign said:

@JerryG - Agreed, but that's way beyond reasonable effort for what should be a reference design (or for our project requirements).

Oh I agree 100%. Not publishing the entire schematic is just a cop-out in my opinion. I don't know what secrets Digilent/FTDI think they're keeping by not publishing an uncensored schematic, but it wouldn't be more than a minor inconvenience to a cloner. What it does accomplish, however, is deprive legitimate users of board information they might need.

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On 5/17/2016 at 11:28 PM, dfergenson said:

wfjmueller, would you (or anyone else) be willing and able to post or link to some code (VHDL ideally but I'll take what I can get) that shows USB communication via the FT2232? I'm trying to get this working but I'm having trouble finding a point of entry. Thanks in advance. -dfergenson

Is now on GitHub as part of the w11 retro-computing project. The serial port handling is under rtl/vlib/serport with

There is a whole stack with elasticity FIFOs

I'm using the later with 120 MHz serial clock and 12 MBaud in many designs.

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