Basys2 FPGA Board - Constraints File

[jotran00]

Hello,

I  appreciate  if you could help me to answer the following questions:

     1. Regarding the clock pin for Basys2 board configured, what is the "CLOCK_DEDICATED_ROUTE" ? and Why is it's setup to "FALSE" condition?.

     2. What is the different between the ("NET "mclk" LOC = "B8";) and the ("NET "mclk" CLOCK_DEDICATED_ROUTE;)

 

Thanks,

Jonathan Tran

 

[hamster]

The FPGA has "a set of components and connections that are designed specifically to carry clocks..

Clocks ar special in that they carry timing information but no data, and because the clock has to 'tick' at the same time all over the chip these are specially designed to have the same propagation delay from the source to all parts of the chip - quickly look at  https://en.wikipedia.org/wiki/H_tree to see how this is done.

When a signal that is acting a as a clock is routed (connected) over the FPGA's regular connection it gets a little out-of-time (skewed), depending where on the chip it is running. For small designs this can work OK as the amount of skew won't cause a design failure, but as the design grows so does the relative skew,..

CLOCK_DEDICATED_ROUTE=TRUE tells the tools that ONLY the clocking networks can be used to carry clock signals - so only the clock signals driven by a Clock capable pin can be used (some pins have a direct connection into the clocking networks).

The CLOCK_DEDICATED_ROUTE=FALSE setting allows clock signals to move between the routing networks without generating an error (unless the design is broken by the predicted amount of skew). 

The settings in the UCF file mean that anything can be used as a clock, but MCLK has the enforced restriction that it MUST use the clocking networks.

It is a little bit more complicated than this... 

[jotran00]

Hello,

Thanks for your responding.

Your formation above helped me more understanding about the functional clock on a FPGA board. I can see the different between clock as the time carrier and the signals as the data carrier that drive  over many sets of components on FPGA board.

Thanks,

Jonathan Tran