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How to use the DDR on Zybo


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Hi all,

   I am currently working on a video processing project and need to store frames of RGB signals into the DDR on the Zybo board.

   But it seems there is not many documents discussing how to use it.

   Here are the material I have read:

      1) Zybo reference manual (doesn't cover much but mentions to read Zynq-7000 manual)

       2) Chapter-10 of Zynq-7000 manual DDR memory controller ( focus a lot on the architecture, but not on how to use it)

       3) The Zynq Book Tutorial  (mentions DDR while introducing processing system)

 

    Can someone give me more directions on how to use the DDR memory on Zybo? Things like what to read or where to find example project will be very very helpful.

 

    Thank you very much!

Hao

 

Edited by JColvin
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Hi,

Here's a more FPGA-centric description of what is going on. i've never done much this but...

The DDR memory is connected to the same AXI bus infrastructure that is used by the ARMs CPUs (a.k.a PS or Processor Subsystem) - but it is on the "far side" from the AXI interfaces onto the FPGA fabric. So to use the DDR in a pure FPGA design you still have have configured the PS, which configures whole AXI bus infrastructure, then tell the CPUs to do nothing.

There are a few options for the interfaces onto the FPGA fabric

- A General purpose slave port - all the transactions come from the PS and into the fabric from the CPUs. This is great for implementing a "register file" or memory mapped I/O. The access is best for CPU-word-sized transfers

- A General purpose master port = this allows the FPGA design to issue read and write transactions against other devices on the AXI bus. This is how an FPGA design would write a  few words to DDR, but is not designed for high bandwidth writes.

- There is another port (called something like ACP) which logically connects between the CPU and it's cache, so is the one you would use if you were assisting the CPU with fine-grained processing. You don't want to use this too much as your read/write transactions will push data in or out of the CPU cache. For example, continuously writing MBs or video data will completely thrash the cache and destroy CPU performance.

- A high performance master ports. These sit close to the SDRAM and are designed for performing large transfers rather than single-word access. Think DMA for video ore NIC traffic.

The AXI protocol is pretty hard to learn but simple to use. It is hard because it has to support a lot of features making the documentation quite verbose and confusing with lots of terms and ports that you have to research. It is simple to use because usually you only use a subset of the features available unless you are doing something really complex.

However, AXI IP cores are quite easy to use, but as they support all the bells and whistles they can be very large compared to a striped-out bare-metal AXI implementation.

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Some updates about my question:

Below are 3 IPs I found related:

a) AXI Direct Memory Access

b) AXI Video Direct Memory Access

    (Figure-3 on Zybo Manual points out that the DDR Controller is connected with Programmable Logic through "High Performance AXI ports")

 c) Memory Interface Generator

    (found in Vivado IP Catalog)

 

I am so confused about the above 3 IPs. Which one should I use to access DDR?

 

Thank you!

 

Evocati

 

 

Edited by Evocati
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Hello Evocati,

I had the same problem when I was researching your support question.  I am sure there is some documentation somewhere on how to read and write from the DDR in a bare-metal application but I cannot find it.

Then I remembered that SDK has a memtest application in their demos.  Check that out.  In there your can see how the memtest application just uses the base address to index into memory that you can read and write from.

 

The specific line you are looking for is

            *(Addr+I) = Val;

in the "xil_testmem.c" file.

Good luck!

Marshall

 

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Thank you JColvin, Marshall and Hamster!

Your replys are very helpful.

I think my first step should be learning AXI and trying to configure PS. Then I will study what signal I should put on the AXI interface to read/write the DDR.

 

Evocati

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