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ntallen

Nexys4 Spi Flash

Question

In section 3 of the Nexys4 manual, it says:

 

An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data.

 

I spent some time trying to figure out how to accessthat available space but was thwarted by the fact that the configuration clock output at E9 is dedicated for use during FPGA configuration, so I can't drive it in my design to access the flash.

 

Is there a work around for this that would actually make it possible to access this extra space?

 

Edited by Josh
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CCLK is actually a "shared" I/O with configuration, which means you can drive it after configuration has completed. The trick is that you need to instantiate a STARTUPE2 primitive in order to access it (I believe this requirement is new to 7series devices). EDIT: Just saw that you already tracked this down,jtonfat. I would try connecting your SCK signal to USRCCLKO, and '0' to USRCCLKTS, and then leave all other signals disconnected, to see if defaults will work. I've never actually used this primitive before, so I'm not going to guarentee this will work out of the box...

 

If you really want to save yourself alot of trouble, I recommend creating a microblaze design and using Xilinx's "AXI Quad SPI" core. That core can internally instantiate the STARTUPE2 primitive, and has software examples for accessing Quad SPI flash.

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Hello,

I am also with the same problem. In the Nexys4 manual, it is only mention that the SCK pin is mapped on the E9 pin. But when I tried to select this pin for my design, it is not possible because this pin is dedicated for configuration.

I found this: http://forums.xilinx.com/t5/7-Series-FPGAs/Driving-CCLK-with-user-logic/td-p/296421

But I am not sure how to use the STARTUPE2 primitive. Should I only map my SCK pin in this primitive and leave all other pins unconnected?

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I did get this working, so don't give up hope. I am using XPS in my design, so I can tell you how I got it to work, but if you're doing something different, that might not help so much. Are you using XPS?

 

I will try to follow up tomorrow with more details.

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Hello!

I am not using XPS. I am trying to do my own dynamic reconfiguration manager with a small area overhead. I found this regarding the instantiation of the STARTUPE2 primitive. (page 6 mention how to connect this module to access the SPI flash)

http://ohm.bu.edu/~dean/Xilinx/KCPSM6_Release7_30Sept13/Reference_Designs/SPI/KC705_KCPSM6_SPI_Flash_reference_design.pdf

But I have tested, and nothing. I also try to simulate my design but I had a problem that I think is related to ISE. I am planning to test in Vivado.

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Can you elaborate on the behavior your design exhibits? If possible maybe try creating a design that only instantiates the STARTUPE2 primitive and just connects the 100MHz clock to the output. Then if you have a scope handy, try scoping the pads of R216 or R227 (unloaded resistors attached to the CCLK pin, can be found on the underside of the board next to IC11). If you see the clock, then the STARTUPE2 primitive is working properly and you can move on to debugging other aspects of your design.

 

EDIT: It might be better to just attach the output of a switch to CCLK, and then to just toggle the switch manually after configuration. Then all you will need is a Digital multimeter to run this test. 

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I found working with a logic analyzer to be very helpful in getting my application to work. As Sam suggests, making sure you can at least control the CCLK is a very important first step. After that, you have to work your way up through the protocols required to talk to the device, which are non-trivial.

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I have this working using XPS. I agree completely with sbobrowicz: you need a STARTUPE2 primitive in order to drive the clock. On that primitive, you need to drive the USRCCLK0 (with the clock signal you want to send to the flash) and you need to drive USRCCLKTS to '0' to enable the clock output. Within XPS, this is handled just by selecting the 'Use STARTUP Primitive' option.

 

In my experience, getting the clock to the part was only the first hurdle, but it is clearly an important step.

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Hi!

I achieved to send my clock signal through the CCLK pin using the STARTUPE2 primitive with the following connections:

 

 

   STARTUPE2_inst : STARTUPE2
   generic map (
      PROG_USR => "FALSE",    -- Activate program event security feature. Requires encrypted bitstreams.
      SIM_CCLK_FREQ => 0.0    -- Set the Configuration Clock Frequency(ns) for simulation.
   )
   port map (
      CFGCLK => CFGCLK,          -- 1-bit output: Configuration main clock output
      CFGMCLK => CFGMCLK,     -- 1-bit output: Configuration internal oscillator clock output
      EOS => EOS,                        -- 1-bit output: Active high output signal indicating the End Of Startup.
      PREQ => PREQ,                   -- 1-bit output: PROGRAM request to fabric output
      CLK => '0',                            -- 1-bit input: User start-up clock input
      GSR => '0',                            -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
      GTS => '0',                            -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
      KEYCLEARB => '0',              -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
      PACK => '0',                          -- 1-bit input: PROGRAM acknowledge input
      USRCCLKO => SCLK,          -- 1-bit input: User CCLK input
      USRCCLKTS => '0',              -- 1-bit input: User CCLK 3-state enable input
      USRDONEO => '1',               -- 1-bit input: User DONE pin output control
      USRDONETS => '0'              -- 1-bit input: User DONE 3-state enable output
   );

 

I left unconnected the signals CFGCLK, CFGMCLK, EOS and PREQ. I check the CCLK pin of the SPI FLASH with an oscilloscope to verify it.

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thank you verymuch, I haven't  a complete concept about STARTUPE2. TO be honest,i don't know how to use it .IS it directly copied to the TOP module?

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