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Found 113 results

  1. Hi, If anyone is interested in retro systems I've started on a port of the Multicomp system. I have a 6502 with basic up and running, you need a pmodps2 to use a keyboard (must be a proper ps2 keyboard). SD Card, Serial access, Z80 and 6809 to follow. https://github.com/mattuna15/zed-multicomp Enjoy
  2. I am trying to make RAM work on my zybo; however, it keeps failing the memory test, I have tried https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/ZynQ-DRAM-fails-in-test/td-p/834342/ https://forum.digilentinc.com/topic/15755-ddr-issues-on-zybo-z7-20/ additionally, I have tried setting up different "memory part" in the settings in vivado according to these reference manuals https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual/ https://reference.digilentinc.com/_media/zybo:zybo_rm.pdf Do you know what I might be doing wrong?
  3. Hi. I'm using zynq board. I'm a beginner. In my design, I used aurora8b10b IP (with framing mode) . It has AXI_ tdata, tkeep ,tlast,tvalid port. I controlled these signal in my custom logic. What I want to do is reading a frame data from aurora on the PS side. When I see the axi stream fifo, I have similar ports. Can I use this? Or should we use DMA? Please tell me the proper way. thanks
  4. Hi, While there are many examples showing a basic Hello World using a Zynq UART, how do we read in data from the console using the same UART? Can anyone please guide me to the right example. I cudn't find one.
  5. Hello, I took everyone's advice and I played around with quartus and vivado and honestly I like quartus but I digress. I think I want to get a hybrid SoC/FPGA device to play with instead of plain FPGA. My question is, does the vivado webpack allow for full ARM baremetal development/debugging on the Zynq devices provided by digilent? I found out rather late that Quartus "community" edition doesn't support baremetal development(a ridiculous omission since you're developing an FPGA hybrid but anywho....)
  6. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v
  7. We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
  8. Hi everyone, I am looking for some guidance here: I need to interface my PS processor (user space application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below. I just want to pass some data to my IP (sha256), have the calculation done on PL and return the value to my processor ARM Cortex-A53 on the PS. From a block design perspective, am I missing something? Do I need to add an AXI DMA in between my MPSoC and my AXI interconnect? Appreciate your help
  9. rcjhy8

    Zybo External LED Control

    Hi all, New to the FPGA world as I was tasked a project to help familiarize myself with the programming and function of how FPGAs work. As you can all infer, I am in need of some help on a specific project that I am doing. I am using a ZYBO Zynq 7000 development board, and Vivado 2019.1. What I am trying to do is control an external sensor, or LED through some user interface. I have seen a lot of tutorials that use the on-board LEDs, and if you press a button, it displays that value in binary in a command terminal. My task that I was to do is be able to turn on and off an external LED connected to the ZYBO through the command terminal. It seems I can connect a simple circuit with a LED and a resistor to the PMOD pins that are power and ground. What the command terminal would let me do is then essentially cut power to that pin, therefore turning the LED off. Please let me know if this is probable, and/or how I should task to complete it. Thanks, Russell
  10. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. https://www.dgbwiki.com/index.php?title=FPGA_mining https://www.coinfoundry.org/pool/dgb5 DigiByteCoin Github Odocrypt Mining Software https://github.com/DigiByte-Core/odo-miner It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  11. sgandhi

    Webserver using Zybo Z7

    Hello, I have been successful in running the lwIP echo server on the Zybo Z7 board. However, I want to develop a web server on Zynq. I have gone through the lwIP documentation. However, in the discussion of this topic, I was successful in reading the .bin file from the SD card. Now I want to set up a web server on Zynq so I can command the server to read the .bin file from SD card and store it in the DDR. How do I start working on the web server. I have been searching a lot for the tutorial or anything that could make me understand in a simpler way but I failed to find any.! I also tried understanding the echo server C code in sdk however, after a point it seems too confusing to me. I could even think of modifying the echo server C code to develop a web server with some help, may be. The documentation of lwIP is confusing to me at this point.... Thanks, Shyama.
  12. birca123

    ZYBO Image Processing

    Hello, is there any image processing library that can be used for standalone applications on ZYBO? Thanks, Toni
  13. Hi. I'm beginner of zynq. When I was designing with hdl on spartan6, I drew a timing diagram and designed a state machine to make the desired signal from the desired state. So, I've already designed a state machine. However, I am not sure because I am going to use this state machine in combination with the aurora ip and gpio ip of xilinx. I want to design to interact with gpio1 in some states and gpio2 in others state. (i mean that read value from gpio to PL side in specific state.) For do that, do i design a state machine in custom axi ip? Can i control it only with hdl? Or do I have to control it with C code in SDK? I'm sorry that the question is not clear because I don't know well. Thanks.
  14. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar
  15. Hi! In previous topic i have asked about first start with Zynq core (i have Ettus E310 board) Now it is time for connecting ADC that is on board AD9361 . I want to get some signal and receive it via ADC - i do not understand how to connect ADC (how to edit Zynq for getting data via RF board connector (via LVDS??) https://files.ettus.com/schematics/e310/e310.pdf) I have read manual (p.34) about that ADC https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf I hope, somebody help me to edit blocks or code in Vivado and get digitalized data from ADC. Best regards.
  16. I want to use GNU RADIO to design an RF signal receiving circuit. For this I plan to use an FPGA card in the baseband section of the circuit (to handle the decimation and, if possible, to convert analogue to digital signal). My doubt lies in knowing if it is possible to communicate the FPGA card to the GNU RADIO application directly or if necessary from an external program. At this point it should be noted that I work in windows 10. I'm quite new on the subject of FPGA and GNU RADIO. I would really be grateful if you help me with this problem. The card is a Xilinx Zynq-7000 Developmet Board, the Z-7010, its features are best seen on the next page https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual Suggestions for design changes are welcome. In advance thanks for the help.
  17. Kris Persyn

    Stuck in SDK

    Hi, I'm stuck in SDK. I want to control my hardware design through the use of IP cores, but can't seem to get my software to run properly. I cant even xil_printf nor light some LEDs on my Zybo z20. Any suggestions? head.h helloworld.c
  18. Hi folks, I hope all is well with you. I am a newbie to zynq AP SoC. I started working with Digilent Zybo board, lwip ethernet echo server example. Problems facing. 1. Auto Negotiation failure if i set the link speed to auto in bsp. If i set link speed to 1000Mbps the program says that the ethernet link is down. 2. How to modify the echo server program where i can send and receive data to a specific ip address with specific port number as Server and also as client. I am using a Xilinx SDK version 2018.3 Operating system: Windows 10 Happy to hear a best possible solution from you folks. Thanks in advance. Regards Ajeeth kumar
  19. shurunxuan

    Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for [email protected] like this: static const VideoMode VMODE_3840x2160a30 = { .label = "[email protected]", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  20. I'm trying to boot a Zedboard using a SD card, and it fails. The Power good LED is on, but the 'Done' light remains off. I tried 4 different SD cards (all UHS-I), but later read that UHS-I cards aren't supported, so I'm using a non-UHS card and it still fails to boot. MIO6:2 headers are '01100', which is the SD card boot configuration. I've also shorted JP6 on the board. VADJ is at 1.8V The board boots successfully from QSPI - the blue LED and 4 red LEDs come on. I formatted the SD cards using both: the official SD Card Formatter & Windows 10's inbuilt 'Format' Then I copied the 5 files from the Out-of-box Demo on Digilent's website: https://reference.digilentinc.com/reference/programmable-logic/zedboard/start?redirect=1 I've also tried the 'zedboard_oob_design' from the Avnet forums, and the Analog Devices images from their website - and the board still fails to boot. I've tried the SD cards on another Zedboard, and it fails to boot on that one as well. The UART doesn't print anything (115200, 8N1) either. Is there anything I'm forgetting to check? Does the SD card require a specific format, sector size, partitions etc?
  21. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part193-The-Zynq-SoC-s-EMIO/ba-p/764971 I also found such SD card controller for Nexys4 board, while it seems a bit challenging to get it to work with Arty Z7 board due to different pin mappings. https://web.mit.edu/6.111/www/f2015/tools/sd_controller.v Any help is appreciated. Thanks, Mahdi
  22. hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  23. hello everyone, I need help in hardware requirement for the xmcdma_interrupt_example.c test. I tried below example design as in program it is for 8 channels and the mm2s port is connected to s2mm port. At the output, it is showing Entering main( ).but not going further in the code. please help me with this. thanks in advance, Regards amit
  24. Hi Everyone! I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the clock but its amplitude is Small (around 200 mV compare to the reference voltage of 3.3 V). Moreover, I don't know why, but the clock signal seems to have an offset greater than 1V. I want to know if somebody before me faced the same problem? If yes how did you solve it? The second question I would like to ask is to know if Digilent Engineers checked their pmods on the Zynq 7020? If yes, could you please provide us with a template design as reference to check on our board? Thank you for any suggestions. Hervé
  25. I am trying to boot embedded linux on Zynq Zybo with reference to this document: http://80.93.56.75/pdf/0/7/6/4/8/07648722.pdf I have created boot.bin(containing FSBL.elf, my custom hardware bit file and u-boot.elf) devicetree.dtb, uimage and uramdisk.img.gz in ZYBO_BOOT in sdcard as given. When I tried to boot Zybo inserting SD card in the board, nothing shows in the hyperterminal. Instead of my custom hardware, I have created a boot.bin file from the ZYBO Base System Design (available on the ZYBO product page of the Digilent website). Now it responded but showed the following error in the hyperterminal: MAC Addr: D8 80 39 5C F9 FC No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d initcall sequence 04062bf8 failed at call 04046944 (err=-1) ERROR ### Please RESET the board I think the error is from the u-boot-digilent/lib/fdtdec.c when CONFIG_SPL_BUILD is not defined. But the reason for not defining it is not known! What would be the reason?