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Found 86 results

  1. Hi all, i want to interface RGB(24 -bit) display with zynq 7000. How can I do this. I don't have any idea about how to do this. Can anyone help me .
  2. smit

    Measuring time using a Zynq Processor

    I am working on the Zybo Z7-10 board. My goal is to determine the position and orientation of the FPGA in space at any given instance. For that, I am using a PmodACL2 and PmodGYRO. Now, I need to integrate the accelerations and angular velocities. How do I measure the time at which the Pmods are giving me the data?
  3. deppenkaiser

    New Development Board

    Hello, i need urgently a Zynq board which is able to run petalinux; it must support tcp/ip-select and uio-interrupt. I do not know, which digilent board has the examples that include the needed funtionality. I would buy this board because i Need it for my Masterthesis! If you do not have such a board (with the right examples) then please tell me who such a board sells. Or, you give me please a very simple but complete project with only one gpio (Interrupt) that fits on the Arty-Z7-20 board including a petalinux image with the described functionality. My given time is limited and it is very important to me Thank you...
  4. Simo47

    no console in ttyPS0 : zybo 7010

    Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  5. Hello guys, I am using Zybo Z7-10 and want to use a timer which polls e.g. every 100ms by starting a task in freertos. What is the best way to implement such timer? Do I need to use XScu_Timer or Global Timer or Watchdog Timer Thanks, Mirco
  6. Lars Jeppesen

    Problem with JTAG-HS3 on Zynq7000

    Hi, We have bought two JTAG-HS3 debuggers. One of them works perfectly, but the other one keeps returning: "1 whole scan chain (device configuration stabilizing)" or "1 whole scan chain (device configuration unstable)" when using the "targets" command. Any idea what could be the problem? Best regards Lars
  7. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: http://www.elpcctv.com/mi5100-5mp-usb-camera-module-usb20-aptina-125inch-color-cmos-sensor-100degree-lens-p-221.html CSI-2 Camera: https://www.waveshare.com/product/rpi-camera-f.htm DLP 2000 RGB - projector: http://www.ti.com/tool/DLPDLCR2000EVM HDMI projector: https://www.ebay.in/itm/302673956725?aff_source=Sok-Goog Display : https://www.alibaba.com/product-detail/5-inch-720p-oled-display-720_1925219941.html?spm=a2700.7724838.2017115.42.6ba11d77AqfGq7 Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  8. tekson

    Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  9. tekson

    Linux image for Zybo Z-10

    Hi all, I m a beginner in FPGA. Last month I got a Zybo Z-10 board from diligent web store. Started working on it using Vivado 2017 edition. I played with leds and switches in PL section. Now I want to run linux image on this board. I tried many tuturials which showing how to boot zybo with linux. but failed. As in the tutorials, I created sdcard with two partitions, one with ext4 and another with fat and then I copied devicetree files, boot files etc in one partition and linux files in another partition. When I boot the board with sdcard monitor shows a black screen with some text like petalinux 2015, zybo login etc. Actually i dont know how the it boot up with linux in zybo board. I dont know whether this screen which I got is correct screen or not. Can anyone help me to boot a linux from my zybo z-10 board Thanks in advance.
  10. amurices

    FPGA SPI transfer timed out

    Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; axi_quad_spi@41e00000 { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; spidev@0 { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  11. Hi all, I've recently started to learn / play with Ada using the GNAT GPS 2017 IDE from AdaCore, so far on STM32 systems. I very much like Ada, I hadn't realised that it was such a capable low level development language and as a bonus strongly typed. Anyway, in the free version of GPS, AdaCore supply "small" and "full" Ravenscar run-times for the Zynq. As an experiment, I've used GPS to write some Ada that compiles into an ELF and appears to be correctly built for "Zynq7 Processing System" (in terms of initialisation, vectors etc. Cleaned using an ELF viewing tool). The one thing I can't figure out is how to merge the Ada ELF file with my Vivado BIT file. In Vivado I've built a simple processing example that uses a custom AXI component to operate the LEDs on my Zybo. I've written a C version of my Ada using the Vivado SDK.to make sure the BIT file works. I can finds lots of posts on-line explaining how to merge BIT and ELF files for the MicrobBlaze processor, but nothing for the built-in Zynq ARM cores. I had naively assumed it would be something you could do from within Vivado (you can for the MicroBlaze). I've tried to use the "updatemem" command but have struggled to find some of the input files that it requires and I'm not even sure if it will do what I want. Does anyone have any suggestions? Many thanks! Max
  12. deppenkaiser

    UIO Interrupt handling

    Hello, i have an issue with the uio Interrupt handling. An AXI-GPIO ip core with enabled interrupt is connected with the interrupt system of the Zynq on an Arty-Z7-20 board. With petalinux i created an minimalistic Linux image which is running on that design and gives the GPIO-HW an uio device. I can read and write data throu that GPIO-HW via the Linux uio device. Now i wish to use the Interrupt ability. I know that i must make a blocking read Operation on the uio device to wait for an incomming Interrupt. If i push the "make Interrupt"-Button, then i do not receive an Interrupt (blocking read does not return). The GPIO IP core was configured like on a bare metal System. The "proc/Interrupts" file is empty, so Linux detected no Interrupts. I think that i must configure petalinux (e.g. petalinux-config -c kernel) to process Interrupts with Linux but i do not know which part of the large configuration i should Change and in which way. So here my questions: 1. What are the needed petalinux config items and there values to enable the uio Interrupt handling on Linux (petalinux)? 2. Are there special c function calls to enable the Linux Interrupt ability? 3. Has anybody ever seen an uio interrupt handling application on a zynq and could you give me the example code? 4. Is there a digilent eval board with a demo app uses that Technologie? 5. What is the Price in US-$ to get that informations? Thank you...
  13. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  14. alonzo

    Zybo Ethernet example

    Hello, I have tried to build an Echo Server on Zybo using example from SDK. Because I could not find any hardware examples I followed this one for Arty: https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start I just customized it for Zybo and used Zynq instead of Microblaze. I uploaded the program on my Zybo but Echo server does not work because every time I try to communicate with it I get the timeout. I have read on this forum that it is possible to design Zynq processing system (with Ethernet enabled) as hardware and then the SDK example should work. But I have difficulties in designing the processing system itself because it will not generate a bitstream. Is there a step by step example on how to design the processing system for Zybo or how to set Ethernet interface on Zybo? I would really appreciate any suggestions. I work on Vivado 2015.4 Best regards Piotr
  15. Enrico

    Zynq SPI timed out

    Dear All, Me and a colleague of mine are facing an SPI timeout issue on a Zynq. We already posted the issue in the Xilinx forum: https://forums.xilinx.com/t5/Embedded-Linux/SPI-transfer-timeout/td-p/833550 but we did not receive any answer, yet. So I would like to ask your help. I am trying to use a TFT LCD screen with the Digilent Artyz7, exploiting the frame buffer. I created a project on Vivado that exports the Zynq PS SPI interface through EMIO. I have already deployed the linux-digilent kernel (v4.4.0) on the Zynq and I am able to see the SPI peripheral under /sys/class/spi_master/spi2.0 (the device tree has been generated using SDK). Thus, as soon as I try to insert the kernel module for the frame buffer support, I get the following error: spi2.0: SPI transfer timed out I attach the images from the logic analyzer: The kernel module of the frame buffer sends the data correctly through the SPI interface before going to timeout state. Any ideas or suggestions regarding this issue? Thanks a lot. Best Regards, Enrico
  16. ahmedmohamed85

    FPGA Projects and ZYNQ step by step tutorials

    Hi all, A new website is offering FPGA projects and ZYNQ step by step tutorials with full source codes, maybe it is useful : https://www.fpgagate.com/
  17. StudentAmsterdam

    XADC PS side, zybo zynq

    Dear All, For the first time im trying to get the XMOD working with the PS side and print the values in a terminal. I tried a bunch of tutorials like the microzed chronicles.. I ended up using the tutorial posted as attachment, as attechments I also included my sourcecode and block design. I tried debugging by making several prints and I know the code works untll at least the "Test2" printf. During the build, no errors or anything appear. So i'm a bit confused into finding out where it all goed wrong. xadc.pdf design_1.pdf lab3.pdf
  18. epsilonjon

    Cannot connect to lwIP echo server on PYNQ

    Hi, I am trying to run the lwIP echo server application project template from the Xilinx SDK on my PYNQ board. I have followed this tutorial for the Zybo FPGA board (which also contains the ZYNQ): https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start Everything works fine until the very last step, when I come to connect to the echo server using telnet. The PYNQ is telling my via serial comms that Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 So I followed the instructions in the above link to set up the ethernet connection on my Windows PC with the static IP address 192.168.1.11 using the given netmask. Unfortunately when I come to connect via telnet using Putty, it tells me that the host is unreachable. I have also tried using my Ubuntu PC but I get the same problem. I have tried debugging the echo server in the Xilinx SDK by setting a break point in the recv_callback() function, but it never seems to reach that part of the code, indicating that no packets are ever received from my PC. Does anybody have any idea what I could be doing wrong please? Thanks!
  19. M24

    help with memory mapping on Zynq

    hello, I used the zybo_hdmi_in as reference for my project. I struggled with the VDMA. After some modifications (added image sensor as input) It seems so I have my program code overlapping with the DDR memory of my frame buffer. I found that my design works once I added an offset to the DDR_0_BASEADDRess. Without the offset the VDMA gives an address encoding error. I increased the offset until it works. Now, the printf's are no longer showing... Looking into UG585 (TRM) the VDMA is definetely within the address range 0010_0000 to 3FFF_FFFF and there seem no overlap. Can anyone suggest me a good document where I can learn more about Zynq memory mapping, and observe problems like stack overflow etc? thanks
  20. deppenkaiser

    Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...
  21. ronik

    PMOD with Trenz board

    Hi there, I'm connecting Pmod NAV: 9-axis IMU Plus Barometer with Trenz board (Trenz TE0701-06 + TE0720). I have been following tutorial to add PMOD in the Vivado design. I using Vivado 2016.2 version. But, in the board section, there is no available board component as it is shown in tutorials which is for evaluation boards, like the one below: In my case, there is no board component: Could you help me in how to make connections with Zynq board, I'm currently using? Did anyone came across this? Thanks a lot!
  22. Colin

    Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from http://www.zynqbook.com/download-tuts.html and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me what am i doing wrong despite the fact im doing the tutorial step for step?
  23. Greetings, I am currently working on a Digilent Zybo Trainer Board with a Zynq 7010 chip. Everything works fine from hardware up to software running on the board as long as it is launched directly from the Xilinx SDK. However, the software hangs up indefinitely whenever the Xil_In32() function is called ONLY when booting from non-volatile memory (QSPI flash or SD card). I have followed the prescribed process of making an FSBL, creating a boot image (with (bootloader)FSBL.elf, hw_wrapper.bit, main_project.elf) and programming the BOOT.bin file to flash memory successfully. The FSBL calls the 'ps7_init()' and ps7_post_config()' functions. My research shows that this issue revolves around enabling the level shifters, but as far as I can tell this occurs in the ps7_post_config() function. Any help would be appreciated. Details: Hardware: Zybo Trainer Board (Zynq 7010) Hardware peripherals: XADC Wizard, AXI GPIO Project: standalone C project Vivado 2017.2 Xilinx SDK 2017.2 OS: Windows 7 Enterprise SP1
  24. Hi there I am selling my Zinq-Z1 board ( zynq 7020 ) She is "as new". I put Arty Z7 in the title because these two board are so similar (not the same colour of pcb, and the Pynq has one thing more: a mic) mine is a pynq. My price is 99€ plus shipment , you can find easily on ebay my announce, there are some photos, I also sell on ebay my Spartan 6 board (papilio duo and computing shield) Thx & Regards B.
  25. mosambers

    Using Pmod of PS-Side of Zedboard

    Hello, I am trying to generate a Digital Output by using the Zynq Processing System. I tought using the Pmod would be easy to handle but I am already failing to design the hardware to activate the Pmod MIO. Do you know a (or similar) tutorial for that? Can you give some advises how to realize it? Thank You! Best regards