Search the Community

Showing results for tags 'zynq'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 96 results

  1. avnrdf

    Zedboard does not boot from SD Card

    I'm trying to boot a Zedboard using a SD card, and it fails. The Power good LED is on, but the 'Done' light remains off. I tried 4 different SD cards (all UHS-I), but later read that UHS-I cards aren't supported, so I'm using a non-UHS card and it still fails to boot. MIO6:2 headers are '01100', which is the SD card boot configuration. I've also shorted JP6 on the board. VADJ is at 1.8V The board boots successfully from QSPI - the blue LED and 4 red LEDs come on. I formatted the SD cards using both: the official SD Card Formatter & Windows 10's inbuilt 'Format' Then I copied the 5 files from the Out-of-box Demo on Digilent's website: https://reference.digilentinc.com/reference/programmable-logic/zedboard/start?redirect=1 I've also tried the 'zedboard_oob_design' from the Avnet forums, and the Analog Devices images from their website - and the board still fails to boot. I've tried the SD cards on another Zedboard, and it fails to boot on that one as well. The UART doesn't print anything (115200, 8N1) either. Is there anything I'm forgetting to check? Does the SD card require a specific format, sector size, partitions etc?
  2. Hello, I am trying to develop a simple verilog code on Arty-Z7-10 that writes to the SD card on the PL side, without having to use SDK software. To do so, I believe I need to setup my SD card pins as EMIO in the ZYNQ and modify the constraint file to uses correct pin mapping. However, I wonder if anyone has done such type of coding before and is able to provide me with more detailed information. I found this tutorial which has tried to do same thing with SPI, but it was not very detailed. https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part193-The-Zynq-SoC-s-EMIO/ba-p/764971 I also found such SD card controller for Nexys4 board, while it seems a bit challenging to get it to work with Arty Z7 board due to different pin mappings. https://web.mit.edu/6.111/www/f2015/tools/sd_controller.v Any help is appreciated. Thanks, Mahdi
  3. sungsik

    ethernet communication with ZYBO

    hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  4. hello everyone, I need help in hardware requirement for the xmcdma_interrupt_example.c test. I tried below example design as in program it is for 8 channels and the mm2s port is connected to s2mm port. At the output, it is showing Entering main( ).but not going further in the code. please help me with this. thanks in advance, Regards amit
  5. herve

    ADC and DAC pmod on ZYNQ 7020

    Hi Everyone! I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the clock but its amplitude is Small (around 200 mV compare to the reference voltage of 3.3 V). Moreover, I don't know why, but the clock signal seems to have an offset greater than 1V. I want to know if somebody before me faced the same problem? If yes how did you solve it? The second question I would like to ask is to know if Digilent Engineers checked their pmods on the Zynq 7020? If yes, could you please provide us with a template design as reference to check on our board? Thank you for any suggestions. Hervé
  6. I am trying to boot embedded linux on Zynq Zybo with reference to this document: http://80.93.56.75/pdf/0/7/6/4/8/07648722.pdf I have created boot.bin(containing FSBL.elf, my custom hardware bit file and u-boot.elf) devicetree.dtb, uimage and uramdisk.img.gz in ZYBO_BOOT in sdcard as given. When I tried to boot Zybo inserting SD card in the board, nothing shows in the hyperterminal. Instead of my custom hardware, I have created a boot.bin file from the ZYBO Base System Design (available on the ZYBO product page of the Digilent website). Now it responded but showed the following error in the hyperterminal: MAC Addr: D8 80 39 5C F9 FC No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d initcall sequence 04062bf8 failed at call 04046944 (err=-1) ERROR ### Please RESET the board I think the error is from the u-boot-digilent/lib/fdtdec.c when CONFIG_SPL_BUILD is not defined. But the reason for not defining it is not known! What would be the reason?
  7. Embd

    Programming BBRAM on Arty Z7-20

    Hello Everyone, I am trying to get Arty Z7-20 boot from flash with encryption enabled. I am following Xilinx 'XAPP1319' to program AES key to BBRAM. I created MCS boot image with 'fsbl' and 'program_aes_key_bbram' application program(xilskey 6.3 example 'xilskey_bbram_example' for Zynq not ZynqMP) for qspi flash as described in Xilinx 'XAPP1319'. However on booting from SPI flash, BBRAM example print exit message 'BBRAM Example failed' on serial console. On debugging with JTAG, I found it fails while programming BBRAM, in function I have the jumper set to QSPI while booting from flash. Attached is serial console output. Any idea why I am having this issue? bbram_out.txt
  8. tiago0297

    Axi DMA always busy

    Hi, I'm doing a project that uses AXI DMA. I already done my Ip Core, my Block Design e and my SDK code. The problem is that when my program reaches while(XAxiDma_Busy(&axiDma, XAXIDMA_DMA_TO_DEVICE)) it gets stuck. I'm using a Zedboard and Vivado 2017.4. I did a search, found out that it's a very popular problem, but I had no success solving it, so I'm posting here trying to get more help. I'm attaching my sources. Thank you srcs.zip
  9. zengqin3

    Zybo-z7-10, FSBL does not work

    Hi I am trying to run the fsbl and hello world on Zybo-z7-10, but seems like it does not work. When I tried to run the fsbl, it shows the message like this. I build this project step by step learning from a video on youtube, the hardware and software part. I post this link at the bottom. The output in terminal is supposed like this, tell me Boot mode is JTAG, but now it is not. Does anyone know why this happen? If FSBL does not run successfully, the other parts in my project won't work as well since the the clock and interrupts from PS side are not activated. For example, in EnableSampleGenerator, I assign 32 and 1 to GPIO, but when I read from it, they are still 0. Also after I start first DMA transmission, when it finishes, there should be an interrupt, and in the interrupt I start another DMA transmission. Now seems like the interrupt never happens, so I seriously doubt the FSBL does not run properly. Thanks a lot in int main()
  10. Sridhar Prasath Aruppukottai Ganesan

    stdin and stdout for uartlite

    Greetings all, Usually, the default uart for xilinx sdk is ps7_uart1. But I want to use axi uartlite block as my stdin and stdout since I want to redirect the xil_printf statements to uartlite rx pin. Is that possible to change the stdin and stdout to axi uartlite and still view the printf statements in the terminal output???
  11. Hello Everyone, I am trying to get my Arty Z7-20 (XC7Z020) to boot from flash with encryption enabled. If I do not enable encryption, I am able to get this to work. I am using the tool "Create Boot Image" in the Xilinx SDK. I open the encryption tab and check the box labeled "Use Encryption" and provide the "Part name." The Part name I use is "XC7Z020." I have also tried "XC7Z020CLG400", which I found when using that board in a Vivado project. The Boot Image is created just fine, and I am able to program the flash. However, when I power on the FPGA, the done light does not come on and it seems to get stuck booting. I do have the jumper set to QSPI. Any idea why I am having this issue? Thanks, Christian
  12. Hello, I am using Zed board 7000. I want to do Image Processing or basic computation in Zed board on PL side using FPGA. I was a bit confused to start either with a Linux image(PetaLinux or Xillinux) or directly through the Vivado software. Is it possible to do any computation or Image Processing on the PL side using ARM processor only to interface the peripherals(I don't want the computation to be done on the ARM processor). Kindly provide any reference link or tutorial which can address my queries. Thanks in advance. ---Nikith--
  13. Hi all, i want to interface RGB(24 -bit) display with zynq 7000. How can I do this. I don't have any idea about how to do this. Can anyone help me .
  14. smit

    Measuring time using a Zynq Processor

    I am working on the Zybo Z7-10 board. My goal is to determine the position and orientation of the FPGA in space at any given instance. For that, I am using a PmodACL2 and PmodGYRO. Now, I need to integrate the accelerations and angular velocities. How do I measure the time at which the Pmods are giving me the data?
  15. deppenkaiser

    New Development Board

    Hello, i need urgently a Zynq board which is able to run petalinux; it must support tcp/ip-select and uio-interrupt. I do not know, which digilent board has the examples that include the needed funtionality. I would buy this board because i Need it for my Masterthesis! If you do not have such a board (with the right examples) then please tell me who such a board sells. Or, you give me please a very simple but complete project with only one gpio (Interrupt) that fits on the Arty-Z7-20 board including a petalinux image with the described functionality. My given time is limited and it is very important to me Thank you...
  16. Simo47

    no console in ttyPS0 : zybo 7010

    Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  17. Hello guys, I am using Zybo Z7-10 and want to use a timer which polls e.g. every 100ms by starting a task in freertos. What is the best way to implement such timer? Do I need to use XScu_Timer or Global Timer or Watchdog Timer Thanks, Mirco
  18. Lars Jeppesen

    Problem with JTAG-HS3 on Zynq7000

    Hi, We have bought two JTAG-HS3 debuggers. One of them works perfectly, but the other one keeps returning: "1 whole scan chain (device configuration stabilizing)" or "1 whole scan chain (device configuration unstable)" when using the "targets" command. Any idea what could be the problem? Best regards Lars
  19. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: http://www.elpcctv.com/mi5100-5mp-usb-camera-module-usb20-aptina-125inch-color-cmos-sensor-100degree-lens-p-221.html CSI-2 Camera: https://www.waveshare.com/product/rpi-camera-f.htm DLP 2000 RGB - projector: http://www.ti.com/tool/DLPDLCR2000EVM HDMI projector: https://www.ebay.in/itm/302673956725?aff_source=Sok-Goog Display : https://www.alibaba.com/product-detail/5-inch-720p-oled-display-720_1925219941.html?spm=a2700.7724838.2017115.42.6ba11d77AqfGq7 Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  20. tekson

    Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  21. tekson

    Linux image for Zybo Z-10

    Hi all, I m a beginner in FPGA. Last month I got a Zybo Z-10 board from diligent web store. Started working on it using Vivado 2017 edition. I played with leds and switches in PL section. Now I want to run linux image on this board. I tried many tuturials which showing how to boot zybo with linux. but failed. As in the tutorials, I created sdcard with two partitions, one with ext4 and another with fat and then I copied devicetree files, boot files etc in one partition and linux files in another partition. When I boot the board with sdcard monitor shows a black screen with some text like petalinux 2015, zybo login etc. Actually i dont know how the it boot up with linux in zybo board. I dont know whether this screen which I got is correct screen or not. Can anyone help me to boot a linux from my zybo z-10 board Thanks in advance.
  22. amurices

    FPGA SPI transfer timed out

    Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; axi_quad_spi@41e00000 { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; spidev@0 { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  23. Hi all, I've recently started to learn / play with Ada using the GNAT GPS 2017 IDE from AdaCore, so far on STM32 systems. I very much like Ada, I hadn't realised that it was such a capable low level development language and as a bonus strongly typed. Anyway, in the free version of GPS, AdaCore supply "small" and "full" Ravenscar run-times for the Zynq. As an experiment, I've used GPS to write some Ada that compiles into an ELF and appears to be correctly built for "Zynq7 Processing System" (in terms of initialisation, vectors etc. Cleaned using an ELF viewing tool). The one thing I can't figure out is how to merge the Ada ELF file with my Vivado BIT file. In Vivado I've built a simple processing example that uses a custom AXI component to operate the LEDs on my Zybo. I've written a C version of my Ada using the Vivado SDK.to make sure the BIT file works. I can finds lots of posts on-line explaining how to merge BIT and ELF files for the MicrobBlaze processor, but nothing for the built-in Zynq ARM cores. I had naively assumed it would be something you could do from within Vivado (you can for the MicroBlaze). I've tried to use the "updatemem" command but have struggled to find some of the input files that it requires and I'm not even sure if it will do what I want. Does anyone have any suggestions? Many thanks! Max
  24. deppenkaiser

    UIO Interrupt handling

    Hello, i have an issue with the uio Interrupt handling. An AXI-GPIO ip core with enabled interrupt is connected with the interrupt system of the Zynq on an Arty-Z7-20 board. With petalinux i created an minimalistic Linux image which is running on that design and gives the GPIO-HW an uio device. I can read and write data throu that GPIO-HW via the Linux uio device. Now i wish to use the Interrupt ability. I know that i must make a blocking read Operation on the uio device to wait for an incomming Interrupt. If i push the "make Interrupt"-Button, then i do not receive an Interrupt (blocking read does not return). The GPIO IP core was configured like on a bare metal System. The "proc/Interrupts" file is empty, so Linux detected no Interrupts. I think that i must configure petalinux (e.g. petalinux-config -c kernel) to process Interrupts with Linux but i do not know which part of the large configuration i should Change and in which way. So here my questions: 1. What are the needed petalinux config items and there values to enable the uio Interrupt handling on Linux (petalinux)? 2. Are there special c function calls to enable the Linux Interrupt ability? 3. Has anybody ever seen an uio interrupt handling application on a zynq and could you give me the example code? 4. Is there a digilent eval board with a demo app uses that Technologie? 5. What is the Price in US-$ to get that informations? Thank you...
  25. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.