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Found 10 results

  1. Sam Bergami

    Zedboard Zynq 7000 XADC Header

    Is there a way to just input a voltage and read it through the terminal using the XADC Header on the Zynq 7000 Zedboard? If so can this be done using the VP VN pins?
  2. Hi, I've recently bought a Zybo z7010 board and had a go at running the example given here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start#tutorial The bitstream was generated successfully as expected but when I load the application on to the Zynq PS, I observe that: None of the LEDs are lit when the corresponding buttons are flicked. No message is displayed on the UART console when any of the switches are pressed. Can anyone provide some hints on how would I go about debugging the issue? Some info w.r.t my build environment: Bitstream generated using Vivado 2016.4 (Windows 10) Power source: wall (JP7 set to Wall) JP5 set to JTAG. Cable: simple USB cable which came with my smartphone. (When JP5 is set to QSPI, I can see u-boot booting a preloaded busybox image so the cable seems to be working fine.) Please advise. Regards, ahmrah01
  3. Bharath

    Zedboard Zynq 7000 XADC Header

    Hi, I'm trying to measure an external Voltage connected to the AUX0 pin of the XADC header using Zedboard .While measuring the output I find that the voltage is shows higher value by factor 3 or even 4 of the input differential voltage applied. I'm unable to figure out why this is happening. C code file is attached also. I have followed the following thread while performing my project too https://forum.digilentinc.com/topic/4311-zedboard-zynq-7000-xadc-header/?page=0#comment-16891 I have connected AUXP0 to 0.2 V and AUXN0 to GND . Could someone help on this?? helloworld.c
  4. tekson

    Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  5. Hello, I was earlier able to flash LEDs on the Zybo 7010 board following the tutorials. However, I am currently trying to use the Zybo 7010 to flash LEDs which are external to the board. What I am looking at here is getting a constant voltage supply from one of the ports (maybe preferably the Xadc) to power the external LED circuit. I am having trouble getting a block design using the xadc_wiz_0 ip and the axi gpio with the zynq 7000 processor. Any information on this is greatly appreciated.
  6. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  7. (Not sure if this thread should go in Embedded Linux. If so, please feel free to move it) Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand. Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be: Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this: touch output ./streamread /dev/xillybus_datastream output This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000... Info: I generated the XADC using the wizard so I guess everything is properly instantiated. Tests I've run so far: I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well. Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was. This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high? I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it. Thank you (and sorry for the long post )
  8. Sam Bergami

    Zynq 7000 External Mux

    Hi I am trying to use the Zedboard zynq 7000 external mux and I was wondering if anyone could provide me with some detailed information or an overview of what exactly the purpose is of the external mux and how it functions. Thanks
  9. Pallavi

    related to zybo

    Why i am getting this error ? By using the Zybo Board "ERROR: [Labtools 27-2149] File D:/pallavi/Vivado Prgrms/zybo_verifyleds/zybo_verifyleds.runs/impl_1/verifyleds.bit not found. Check file name and file permissions. ERROR: [Labtools 27-2163] Unable to read xicom bitstream D:/pallavi/Vivado Prgrms/zybo_verifyleds/zybo_verifyleds.runs/impl_1/verifyleds.bit"
  10. jcloiacon

    USB on Zybo

    Good afternoon! I am trying to get USB interfacing to work on the Zybo. Because I eventually want to build my own board, I am familiarizing myself with all parts of a functional toolchain. My toolchain looks like this: Generate hardware platform with Vivado 2016.2, using Digilent HW Platform Guide as a reference. Exporting hardware from Vivado. (Note: Hello World SDK project runs successfully from this HW design). Use Petalinux 2016.2 to create a project, load in files as necessary, and generate boot image, as described in UG1144. (Using hdf and bit generated with Vivado, FSBL and Device Tree unchanged from petalinux defaults) Copy BOOT.BIN and image.ub to SD card Linux boots properly, and I have shell access over UART. However, plugging and unplugging USB devices has no effect. By contrast, the prebuilt image provided in this Petalinux BSP repository based on the Digilent Linux BD can detect and identify USB peripherals. The default device tree and kernel configuration *look* complaint with the Zynq Linux USB Xilinx wiki page, with the exception that the device tree lines are divided between zynq-7000.dtsi and pcw.dtsi, and Generic ULPI Transceiver Driver is not an option when running petalinux-config -c kernel. Also, dmesg yields some information when run on the Zynq: root@julianzybo:~# dmesg | grep -i usb usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver usbcore: registered new interface driver usb-storage usbcore: registered new interface driver usbhid usbhid: USB HID core driver but lsusb isn't even present: root@julianzybo:~# lsusb -sh: lsusb: not found Has anyone successfully built Linux from a custom hardware platform, and gotten USB to work? EDIT: I have not connected any reset to USB0, but I do see the line usb-reset = <&gpio0 46 0>; in the Petalinux-BSP repository device tree. Perhaps a USB reset is necessary?