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Found 358 results

  1. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as provided in file Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its specific part edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) i have attach xdc file and desing image i m using zybo board having specific xc7z010clg400-1 part pls provide some solution or any other help ASAP Zybo_B.xdc
  2. mbo

    Zybo and PmodCAN

    Hello members, I have the Zybo-Z7 Board and I want to connect it with other Zybo-Z7 Board via CAN. The board has an integrated CAN Controller and I need following PmodCAN-Connector which has also can controller integrated. http://store.digilentinc.com/pmod-can-can-2-0b-controller-with-integrated-transceiver/ Which CAN Controller shall I use and how do I make it work? I have implemented a basic design for Zybo in Vivado and added the IP core for PmodCAN. Is something more I need? Cheers, mb
  3. Ankit

    USB OTG on Zybo does not work

    @Bianca @Rainer Urian can you help me ? i am also working on zybo board and suffering from same problem. my usb port ( j10 and j9 ) are not getting detected . can you tell me how to resolve this issue ?
  4. elizegi

    Change ZyBo Z7 FT2232 configuration

    Hi, I'm developing a design for the ZyBo and I'm using JTAG to communicate a PC with a microblaze. I'm using the onboard FT2232HQ to achieve this, but it is configured as UART -> Virtual COM Port and 245 FIFO -> D2XX Direct, so I can't see the JTAG connection as a COM port in the PC (which is what I need). I know that this can be changed using FT Prog, but I've seen that a lot of people had problems connecting the board with Vivado after changing the FT2232 configuration. Is it safe to make changes in the FT2232 configuration? Thanks, Xabier
  5. theUltimateSource

    RX / TX LED are swapped on the Zybo

    I know that RX / TX lines for UART connection are going to be swapped at one end or another. but why do you swap them for the status LED that are showing activity? When the Zybo board is sending a message the RX LED lights up?
  6. I see two COMs on device manager for my ZYBO SoC, this is a problem when I want to connect through SDK because it is supposed to have only one COM. Furthermore I have to say that this happens only on my new laptop which has vivado 2018 installed on it, when using my old laptop with vivado 2014 this is not a problem, I see just one COM, and the SDK software runs normally. I can program the bit file, but cannot connect using the SDK and even on laptops that do not have vivado installed, only one COM is shown. How can I fix this issue?
  7. sungsik

    ethernet communication with ZYBO

    hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  8. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip. After installing as described in https://reference.digilentinc.com/vivado/installing-vivado/start I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  9. Hi, I have written a code in Verilog to control screen through VGA port and performed different transitions in color displaying on screen. But now I want to do the same thing from PS part of ZYBO. I don't know whether I have to use HDMI port for this purpose or something else. Please help me out from this problem and suggest me different tutorials to do this task if available Thanks in advance Regards,
  10. Hello, I am new to Zybo/FPGA and currently going thru the tutorial that's available. Currently at the DMA tutorial. From what I understand, there are 2 method to do the project, using SDK or Vivado. When I tried using SDK, I have a whole bunch of missing inlcudes like xparameters.h, xgpio.h, xstatus.h (to name a few). So, I went the Vivado route. When attempting to run the tcl script, I had errors on line 67. update_ip_catalog -rebuild. Was able to resolve that by using the vivado library. Now, I'm stuck with errors stating that IPs are locked. I am trying to follow this recommendation to change the version, but, I can't find the system.tcl file. Any suggestions?
  11. yottabyte

    [Zybo Z7] Which Zynq to choose in Vivado

    please delete. thx /edit
  12. Hi folks! I'm planning to make my own I/O extension board for the ZYBO, connecting directly through JB to JE. Therefore I need the exact dimensions of the board itself and the exact location of the connectors JB to JE in respect to let's say the left edge of the board. Is there somebody around that could provide that information? Thanks in advance. Thomas
  13. Baskoud

    ZYBO license/voucher in Europe

    Hello all, I use ZyBo for a long of time and now that my license expired I want to update it. I live in France and I haven't found a provider that gives just a voucher to continue using Vivado/Vivado HLS and SDK. I found some websites like this https://www.digikey.fr/product-detail/fr/digilent-inc/240-067/1286-1051-ND/4840817 that provide the voucher but plus staff that I don't need. Is there a place where I can buy the voucher/license without anything else here in Europe. Thanks in advance, Spyros
  14. Hi. i'm newbie in electronic engineering. i start to study soc with zybo. When i saw schemetic of ZYBO, i founded some symbol that i have not ever seen. i attached picture. what does red symbol mean?
  15. hello everyone, I need help in hardware requirement for the xmcdma_interrupt_example.c test. I tried below example design as in program it is for 8 channels and the mm2s port is connected to s2mm port. At the output, it is showing Entering main( ).but not going further in the code. please help me with this. thanks in advance, Regards amit
  16. Scarlet

    Zybo Z7-10 with Linaro

    I am trying to boot Linux with Linaro file system on Zybo Z7-10 without Petalinux. I would like to connect a monitor to HDMI TX output to be able to see Linaro graphical interface but I am getting errors while Linaro Ubuntu is booting, and nothing is being shown on the monitor. I am sure that HDMI output works on my board since I got HDMI demo project to work. I am using Zybo base system design from here, adapted to Zybo Z7 on Vivado 2018.2. I have generated device tree from this design using Xilinx SDK following this tutorial. I am using Digilent's u-boot and Linux kernel and I've downloaded Linaro file system from here (last file). These are the errors that are showing up when Linaro Ubuntu is booting: systemd-bootchart.service failed. [ OK ] Started Remount Root and Kernel File Systems. [ OK ] Started Create Static Device Nodes in /dev. Starting udev Kernel Device Manager... Starting Load/Save Random Seed... [ OK ] Reached target Local File Systems (Pre). [FAILED] Failed to start Load Kernel Modules. See "systemctl status systemd-modules-load.service" for details. systemd-modules-load.service failed. Starting Apply Kernel Variables... [ OK ] Started udev Coldplug all Devices. [ OK ] Started Increase datagram queue length. [FAILED] Failed to mount Temporary Directory. See "systemctl status tmp.mount" for details. [FAILED] Failed to start RealtimeKit Scheduling Policy Service. See "systemctl status rtkit-daemon.service" for details. My goal is to enable HDMI output on Zybo Z7. I suspect that these errors are the cause of the problem, but I am not sure if there is any additional step I need to perform to get HDMI to work, like enabling some drivers in Linux kernel, or configuring the device tree. I have tried using different Linux kernel versions (by checking out different tags from Digilent's repository), using different versions of Linaro file system, using default device tree for Zybo Z7 provided with Linux kernel, but I've had no success since various errors are always showing up. I would appreciate any help or someone pointing me in the right direction, since I am not sure what is the cause of the problem. Thank you!
  17. JF_Stephen

    First question on here.... [Zybo DDR]

    OK... I've pored over the forums, and found many questions tangentially related to my topic, yet cannot figure out the answer to my question. I'm using the *original* Digilent Zybo board, i.e. it has a VGA port. I've used one personally for a while now, but I'm now doing a project at work on a new Zybo. I cannot, for the life of me, get the DDR to be configured to work properly. I have tried every which way... including a custom memory part but it is all to no avail. I tried to get around this by using OCM, and it works, but then I could not get the QSPI to flash with my execute in place linker script... something I've done several times for work on the Zedboard. Can someone please help me with the correct DDR configuration so I can get this out from over my head? I'm attaching the current DDR configuration... any help is greatly appreciated. Thank you!
  18. I am trying to boot embedded linux on Zynq Zybo with reference to this document: http://80.93.56.75/pdf/0/7/6/4/8/07648722.pdf I have created boot.bin(containing FSBL.elf, my custom hardware bit file and u-boot.elf) devicetree.dtb, uimage and uramdisk.img.gz in ZYBO_BOOT in sdcard as given. When I tried to boot Zybo inserting SD card in the board, nothing shows in the hyperterminal. Instead of my custom hardware, I have created a boot.bin file from the ZYBO Base System Design (available on the ZYBO product page of the Digilent website). Now it responded but showed the following error in the hyperterminal: MAC Addr: D8 80 39 5C F9 FC No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d initcall sequence 04062bf8 failed at call 04046944 (err=-1) ERROR ### Please RESET the board I think the error is from the u-boot-digilent/lib/fdtdec.c when CONFIG_SPL_BUILD is not defined. But the reason for not defining it is not known! What would be the reason?
  19. greedyhao

    Timing constraints are not met.

    Hello, When I following The Zynq Book Tutorials(exercises 5b) , I met a error unfortunately. It says that 'Timing constraints are not met.'. I have no idea how to solve it. Could anybody do me a favor. timing_1.rpx ------ More detail shows below:
  20. I am trying to access the audio codec SSM2603 on ZYBO over i2c interface from linux user-space for some register get and set, what i did so far I enabled in the device-tree PS I2C_0 in system-user.dtsi &i2c0 { ssm2603: ssm2603@1a{ #sound-dai-cells = <0>; compatible = "adi,ssm2603"; reg = <0x1a>; }; i2cdetect -l output i2c-1 i2c Cadence I2C at e0004000 I2C adapter i suppose i2c coec should appear on address 0x1a but nothing i2cdetect -y -r 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if i add the codec drivers in my kernel snd_soc_ssm2602_i2c.ko and snd_soc_ssm2602.ko the i2cdetect -y -r 1 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- -- which means the i2c device is detected on 0x1a address but its been used by the driver. what i want to do is to make the raw i2c register get /set using i2cget/i2cset but the codec didn't appear without driver, any clue?
  21. hi everyone, i download the example hdmi_in and i'm tryong to open it with vivado but while i'm running the tcl script occurs this error: ERROR: [BD 5-216] VLNV <digilentinc.com:ip:axi_dynclk:1.0> is not supported for the current part. ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors. while executing "create_bd_cell -type ip -vlnv digilentinc.com:ip:axi_dynclk:1.0 axi_dynclk_0 " (procedure "create_root_design" line 50) invoked from within "create_root_design """ (file "../src/bd/system.tcl" line 1669) while executing "source $origin_dir/src/bd/system.tcl" (file "C:/Users/Damiano Balzani/Documents/zybo/Progetti/2015.4/hdmi_in/proj/create_project.tcl" line 102) can you help me?
  22. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  23. Hi everyone, I'm working on a project in which I've to store data that've been read from SD card into the BRAM in SDK (PS). and read that data from PL in Vivado. The question is how should I connect the BRAM Generator IP with the ZYNQ7 PS IP to give the BRAM access in PS.
  24. Hello, I am new in zybo. I am using Vivado 2018.2. The platform is Ubuntu 18.04. I met a trouble when I following the Zynq Book Tutorials, the first exercise , step by step. The tutorial seemed to be fine before I launched the program on hardware(GDB). The LED didn't blink at all. I googled for a while, but no results Here is the picture of my board. The following is my SDK Log. 12:11:42 INFO : Connected to target on host '127.0.0.1' and port '3121'. 12:11:42 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279539437A" && level==0} -index 1' command is executed. 12:11:45 INFO : FPGA configured successfully with bitstream "/home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/first_zynq_system_wrapper_hw_platform_0/first_zynq_system_wrapper.bit" 12:11:52 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279539437A" && level==0} -index 1' command is executed. 12:11:52 INFO : 'fpga -state' command is executed. 12:11:52 INFO : Connected to target on host '127.0.0.1' and port '3121'. 12:11:52 INFO : Jtag cable 'Digilent Zybo 210279539437A' is selected. 12:11:52 INFO : 'jtag frequency' command is executed. 12:11:52 INFO : Sourcing of '/home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/first_zynq_system_wrapper_hw_platform_0/ps7_init.tcl' is done. 12:11:52 INFO : Context for 'APU' is selected. 12:11:52 INFO : Hardware design information is loaded from '/home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/first_zynq_system_wrapper_hw_platform_0/system.hdf'. 12:11:52 INFO : 'configparams force-mem-access 1' command is executed. 12:11:52 INFO : Context for 'APU' is selected. 12:11:52 INFO : 'stop' command is executed. 12:11:52 INFO : 'ps7_init' command is executed. 12:11:52 INFO : 'ps7_post_config' command is executed. 12:11:52 INFO : Context for processor 'ps7_cortexa9_0' is selected. 12:11:52 INFO : Processor reset is completed for 'ps7_cortexa9_0'. 12:11:53 INFO : Context for processor 'ps7_cortexa9_0' is selected. 12:11:53 INFO : The application '/home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/LED_test/Debug/LED_test.elf' is downloaded to processor 'ps7_cortexa9_0'. 12:11:53 INFO : 'configparams force-mem-access 0' command is executed. 12:11:53 INFO : ----------------XSDB Script---------------- connect -url tcp:127.0.0.1:3121 source /home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/first_zynq_system_wrapper_hw_platform_0/ps7_init.tcl targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279539437A"} -index 0 loadhw -hw /home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/first_zynq_system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] configparams force-mem-access 1 targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279539437A"} -index 0 stop ps7_init ps7_post_config targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279539437A"} -index 0 rst -processor targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279539437A"} -index 0 dow /home/greedyhao/LearningAndWorking/first_zynq_design/first_zynq_design.sdk/LED_test/Debug/LED_test.elf configparams force-mem-access 0 ----------------End of Script---------------- 12:11:53 INFO : Context for processor 'ps7_cortexa9_0' is selected. 12:11:53 INFO : 'con' command is executed. 12:11:53 INFO : ----------------XSDB Script (After Launch)---------------- targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279539437A"} -index 0 con ----------------End of Script---------------- 12:11:53 INFO : Disconnected from the channel tcfchan#13. I would very grateful if someone can help me get through this problem.
  25. Guacamoleroger

    Linux on Digilent boards

    Hi, guys, I am in need of a Digilent board to run Linux with a GUI to have access to IOpins and peripherals, and also to work together with the vhdl codes on the FPGA. I am not sure how to install Linux on SD card, start a boot from there, ANDhave at the same time a vhdl code running on FPGA that I could edit and compile using the vivado (2018.2). The idea is to have the vhdl code running the hardware and the GUI on linux to present values of input, output, make the configuration on-line of the vhdl variables, etc... I was thinking about the Zybo board. Can someone give me, please, some directions and/or suggestions? Regards,