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Found 303 results

  1. Hello, i have been searching for a ready to use image to boot form a zybo. where i can make a bootable sdcard just like this e.g.: dd bs=4M if=/path/to/zybo.iso of=/dev/sdx I tried building it with the peta linux guide. This is old and deprecated. Peta linux is missing from the Xilinx website if you dig a little bit deeper you get to the download site for this peta linux. I couldn't find anything there. Isn't there some prebuild image for this hardware somewhere ? Thank you very much.
  2. Zybo hdmi in demo project resolution issues.

    Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. Regards- Shuvo
  3. JTAG programming time for ZYBO

    Hi, dear Digilent experts, We would like to know the avg bitstream download time through UART/JTAG USB cable over ZYBO platform. Since some students reported it took 10 mins around to download new bitstream for very small design (hundreds F.Fs.) which only uses the PL. Would you please help to comment the avg download time through UART/JTAG USB cable over ZYBO platform in your tests ? If it really takes 10mins, are there alternative way to accelerate the bitstream time ? If we don't use the PS and only use PL for design, can user use SD card for bitstream ? Thanks All the best, Nan-Sheng
  4. Zybo Z7 Pcam 5C Demo - AP transaction error

    Hello, I am executing the Zybo Z7 Pcam 5C Demo example program using Vivado 2016.4 and I'm getting an - AP transaction error. Error while launching program: Memory write error at 0x100000. AP transaction timeout Below is the demo program. Kindly help! 14:06:13 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351A6CA01A" && level==0} -index 1' command is executed. 14:06:13 INFO : 'fpga -state' command is executed. 14:06:13 INFO : Connected to target on host '' and port '3121'. 14:06:14 INFO : Jtag cable 'Digilent Zybo Z7 210351A6CA01A' is selected. 14:06:14 INFO : 'jtag frequency' command is executed. 14:06:14 INFO : Sourcing of 'C:/Users/alex/Desktop/Zybo-Z7-20-pcam-5c/sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. 14:06:14 INFO : Context for 'APU' is selected. 14:06:14 INFO : Hardware design information is loaded from 'C:/Users/alex/Desktop/Zybo-Z7-20-pcam-5c/sdk/system_wrapper_hw_platform_0/system.hdf'. 14:06:15 INFO : Context for 'APU' is selected. 14:06:17 INFO : 'stop' command is executed. 14:06:17 ERROR : AP transaction error, DAP status f0000021
  5. How to access GPIO on OS: Linux

    Hello, I create project on SDSoc 2015.4 using platform ( and I select Operating System is Linux because I use about image processing. but I want to access 4 LEDs on PL. Can I access the LED on PL? How to access GPIO (e.g. LEDs) on OS: Linux Previously I used OS: Standalone project. I can access by Xil_Out32(XPAR_AXI_GPIO_LED_BASEADDR, 0x2); but on Linux I can't. Thanks in advance
  6. Hi, I'm kind of new to using external I/O connections on FPGA boards but I'm tasked with a project where I plan to interface a high-speed camera with 6 lvds pairs (4 data + 1 clock + 1 sync) with the clock input reaching up to 360 MHz, translating to a max data flow of 720Mbps through each of the 4 data pairs. Although this is the optimal operating condition, I don't necessarily have to achieve such speeds if I can get something close to that using an inexpensive board as low-cost is an important factor here. I was told to look at the following xilinx fpga boards with the Zynq 7000 series chips: Zybo (~$200): 512 GB DDR3, has VGA and HDMI, only pmod I/O connectors. From what I've read, I understand the high speed pmods are set to 3.3V, but can work at a lower voltage if only used for input, but do I need to physically alter the board for this? What speeds can I actually reach through these connectors? MicroZed (~$200): 1 GB DDR3, no display out, will have to connect through microheaders on the back, but I can control the I/O bank voltages through the inputs from my carrier card for LVDS. MicroZed manual says "Differential LVDS pairs on a -1 speed grade device are capable of 950Mbps of DDR data" but does this mean the microheader connector is also capable of this rate? I ask this because a similar board from MYiR, the Z-turn (~$100), is very similar in design (but includes HDMI and surprisingly much cheaper) and their support says "Z-turn Board expansion connectors are most for PL ports which can support LVDS differential input, the speed is up to 200MHz in theory." which seems too slow. From what I've gathered, the Z7010/20 chips and the DDR3 ram are very capable of handling the speeds necessary for operating the camera sensor and the large ram size is important for storing the large number of frames, but I'm confused whether the board these are on allows these chips to receive the input fast enough to make full use of both these chips and the camera sensor. Are there any other low-end boards with large enough memory and fast I/O that can make full use of this camera sensor? Any help or guidance is much appreciated on where to look and how to design. Thanks.
  7. HDMI doesn't seem to work - no signal

    I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  8. Adding custom IP in Zybo HDMI demo project

    Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  9. UART FTDI chip

    i tested a uart verilog design working great on the zybo at 9600 bits/s, i can communicante with externel MCU's, now i want to send and recieve some data from my laptop. for that i want to use the onboard ftdi chip on the zybo, is it possible to access to MIO pins and write uart data the chip inputs ? thank you
  10. Bonsoir, Je suis entrain de faire un petit projet avec la carte ZYBO. Et vu que 'c'est ma première utilisation de cette carte, j'ai eu des problèmes et j'aimerais bien que vous pouvez m'aider. Mon problème c'est : Comment je peux contrôler une interface graphique créer sur QT avec les différents composant de la carte ( buttons, leds et switchs ) . Par exemple : Lire les état des leds et des switchs . ou par exemple, quand je clique sur un bouton, un checkbox sera coché sur mon application. J'ai installé Xillunix 2.0-Beta comme système d'exploitation pour la carte. Merci d'avance, Translation for English readers: Good evening, I am doing a small project with the ZYBO card. And since 'this is my first use of this card, I had problems and I wish you could help me. My problem is: How can I control a graphical interface create on QT with the various components of the map (buttons, leds and switches). For example: Read the status of leds and switches. or for example, when I click on a button, a checkbox will be checked on my application. I installed Xillunix 2.0-Beta as the operating system for the card. Thank you in advance,
  11. Hi, I am trying to implement xadc on my Zybo Board. I created the hardware and exported it to SDK. Then, I build an application for reading the on-chip sensor. But when I run the application, it stucks at XSysMon_CfgInitialize function. On debugging, I found that it is enabling DataAbortInterrupt. Does anyone have an idea abou this? Please find attached my hardware design, code, address editor tab screenshot and the tutorial that I followed to do it. Thanks & regards Vishav xadc_code.txt lab3.pdf
  12. Zybo placing error

    i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period ); the log file is attached , thank you implem_log.txt
  13. Error customizing/repackaging dvi2rgb IP

    Good morning, I am currently working on a project that uses the DVI2RGB IP on a custom-built PCB like the zybo-z7 board (but uses the zynq 7020 like the zed board) and would like to make my own version of the IP for several reasons but have encountered the following errors: 1) My PCB board has 2 HDMI ports configurable as sink/source, however when using 2 instances of the DVI2RGB core I get the following error: (error1.png) 2) I would like to make a generic data protocol around the HDMI connector that doesn't require blanking and the DVI2RGB core is a nice, open-source platform for me to experiment with new configurations. However, when repackaging the IP regardless of whether I make any changes I get the following error: (error2.png) For 1) I know I can solve my problem by modifying the IP (and probably just by adding a top-level constraint file to overwrite the dvi2rgb.xdc file), but because of the error in 2) I cannot accomplish this task. I have searched these forums as well as Xilinx with no luck regarding this problem. I have also searched through the Xilinx documentation (UG1118) on IP packaging, but was unable to find any useful information about something I may be doing wrong. I have also tried modifying the IP every way I can think of to remove the dependency on the board.xit file, but with no luck. If anyone has tried this or encountered similar problems with modifying any Diligent IP your advice would be greatly appreciated! Just to reiterate, I only really care about being able to repackage the dvi2rgb core myself, and the error above appears simply from editing the IP in the IP packager, leaving everything set as its default and repacking it. The first time I open the IP there is no implementation file group and the file utils/board/board.xit doesn’t exist, but when I repack it I get the error and when I reopen it in the ip packager again the file is there: (ippackager.png) Some info on my setup: I am running windows 10 64 bit, using vivado 2017.1 and have tried this with both dvi2rgb 1.6 and 1.9. If any additional information is needed please let me know. In the upcoming semester I will be helping mentor a group of undergraduate students on the contents of this IP, so resolving this before the semester starts would be a huge help. Best regards, Tyler Browning
  14. cannot connecto to terminal on Zybo Z7

    Hello, just plugged in my new Zybo Z7 471-015 but cannot connect to serial port. It works on the Zybo. PROG UART is connected to USB PC BSP stdin, stdout is set to ps7_uart_1 I have no other application open that is accessing the serial ports to make sure I dis- and reconnected the Zybo Z7, still doesn't appear on the port list Zybo Z7 appears as USB Serial Converter A and B in the device mngr restarted PC tried another USB port replaced USB cable, both are data cables JP6 is set to USB JP5 is set to JTAG drivers had been installed with Vivado 2017.2 re-installed Vivado 2017.2 cable drivers, restarted PC USB port should be listed even without any PL configuration loaded, right?
  15. zybo DVI to RGB

    I have been trying to use digilent DVI to RGB IP for zybo board, the pixel clock from the ip gives an output of 100MHz , is there any way to reduce the pixel clock frequency , if so can someone please tell me how.
  16. dedicated HDMI ports on the Zybo Z7

    hello, The Zybo Z7 has 2 HDMI ports, RX and TX. On the Zybo you had one port which could serve as input or output. Since the PHY is still implemented in the FPGA I wonder what the advantages are with this change, because before you could have set the ports as input or output as you like.
  17. Video Processing using Zybo Z-7010

    Hello, I am doing project on Video Processing. I have installed Linaro on Zybo usnig SD card. I want to use both PL and PS for video processing such that my OS will take the video from camera using USB or HDMI and my PL side will do further processing. Now I am having doubt regarding how I will send the video stream from OS side to PL side for further processing.The one thing I now is that I have to use AXI interface but don't now how to process further.
  18. Hello, I was earlier able to flash LEDs on the Zybo 7010 board following the tutorials. However, I am currently trying to use the Zybo 7010 to flash LEDs which are external to the board. What I am looking at here is getting a constant voltage supply from one of the ports (maybe preferably the Xadc) to power the external LED circuit. I am having trouble getting a block design using the xadc_wiz_0 ip and the axi gpio with the zynq 7000 processor. Any information on this is greatly appreciated.
  19. Zybo and PmodCAN

    Hello members, I have the Zybo-Z7 Board and I want to connect it with other Zybo-Z7 Board via CAN. The board has an integrated CAN Controller and I need following PmodCAN-Connector which has also can controller integrated. Which CAN Controller shall I use and how do I make it work? I have implemented a basic design for Zybo in Vivado and added the IP core for PmodCAN. Is something more I need? Cheers, mb
  20. PMODGPIO build on Zybo (2016.4)

    I am attempting to build upon the hdmi demo, here is what I want to accomplish: Take over PMOD_C port as a general purpose digital output (8 pins) Here is what I have done (aside from debugging for hours) I dropped down and wired a PmodGPIO_0 block in my design and connected it to PMOD_C (JC), used the auto-connection automation function in Vivado. The build seems to work just fine, exported hardware, etc as normal. In SDK I get a drivers/ directory in hw_patform_1 with PmodGPIO_v1_0 and everything looks fine. Here are the exact steps I followed from here to where I am now: copied PmodGPIO.h down to hdmi/src (build project directory) copied code (functions) from PmodGPIO.c into video_demo.c (build main .c) copied code (init, main, close) from output_demo.c into appropriate places in video_demo.c Question 1) The code would not execute, because it appears the XPAR_ for PMODGPIO does not feed correctly into xparameters.h. Is this normal? I tried to workaround by checking system.hdf and found the base address for my PMODGPIO 0x40000000 and hard-coded it. This would allow the code to compile, but it does not run correctly, it hangs in GPIO_begin on the statement Xil_Out32(InstancePtr->GPIO_addr+4, bitmap);. This is the first statement where it attempts to write to the mapped memory. I have a feeling that something with the PmodGPIO IP is not building correctly for me, but I don't know how to correct it. I have tried several times to clean and rebuild the project, but again I don't know if I am taking the right steps. Question 2) Is there some type of 'build' that I need to do in SDK or somewhere else to initialize the IP correctly and be able to write to the PmodGPIO ? Thanks!
  21. My first Zybo/7010 project

    Greetings fellow FPGA enthusiasts! I'm looking for eyeballs Specifically digital logic enthusiasts, HDL or otherwise, and maybe even those appreciative of retrocomputing (my first Zybo project is a C64 clone after all). It is my hope I might find some people interested in this project: and perhaps also the associated "Inside the Box" YouTube channel where I am going to attempt to explain aspects of the project to others attempting to learn. I'd like to break that feeling that I'm the only one in the world interested in these things (I know I'm not but experience and YT video visitor stats keep trying to tell me otherwise ).
  22. So I have come to the conclusion that My Zych/Zybo dev board has been stolen or misplaced. I am wandering if the "node locked" (OR) "device locked Xilinx Dev packages that I purchased will work I I get a new board of the same make as model. I had the zync 7010. What to do, what to do? Since I have been spending more time on configuring the LimeSDR I revived about the same, I time hadn't even gotten a chance to do more than read the setup instruction and config. the tools for the Zync in Vivado. I' still not sure if I should spring for the Simulink tools for DSP and SDR applications even though I am learning this DSP stuff on my own and the math can be intimidating. Can anyone provide any advice? Is there another product out there that would be better suited to my DSP SDR applications. I also want to build a toxin monitoring system. No clue where to start on that one. Thanks in advance. Brian S.
  23. Can ILA work over Ubuntu boot from SD card in ZYBO ?

    Hi, I observe that there has JP6 and J12 for JTAG in ZYBO but no any connector soldered in place. Would you explain when and how to use the JP6 and J12 in ZYBO ? Why does the two connectors are not soldered by Digilent ? Does Digilent expect user not use them ? Why ? Thanks All the best, Nan-Sheng
  24. Hi, dear experts, We use SD card mode to boot the Ubuntu Linux System from ZYBO with USB-JTAG cable for power supply and it works well. However, now we would like to debug HW logic in the PL of ZYBO via Vivado ILA while Ubuntu is running over PS of ZYBO. Thus, I want to ask how to make the ILA work under the use case. According to the Zybo Reference Manual: The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features into a single device allows the ZYBO to be programmed, communicated with via UART, and powered from a computer attached with a single Micro USB cable. Nevertheless, I'm still not quite sure if it can support SD card booting and use of Vivado Hardware Manager via ILA through the same USB-UART/JTAG cable to debug the logic in the PL in ZYBO while Ubuntu Linux is running. Are there anyone having the experience of use case I mentioned ? Or do user need to use separate JTAG cable like J12 for ILA in ZYBO ? or the existing UAB-JTAG cable for power supply can also be leveraged while using ILA debug under the SD card booting scenario ? Please advise or suggest where I can obtain the related resolution or better way to debug via ILA under the scenario. Thanks All the best, Nan-Sheng
  25. Hi, I want to understand the main difference when programming a board which is configured using a BSP (Ex: ZYBO) and which is configured using only device details(Ex: xc7z010clg400-1). I'm asking because I'm configuring only zynq in the block design with uart1 for hello world application. If I program using ZYBO bsp it works but not if I use only the device details. I need to understand this since my actual project is on a custom z7010 board and not a regular development board and I'm not able to get the uart up and running. I wanted to figure it out on a development board as it is easier to understand. I think it is some simple settings detail that I'm missing. Appreciate any help.