Search the Community

Showing results for tags 'zybo'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Calendars

  • Community Calendar

Found 261 results

  1. Zybo: Access the LD_MIO LED from the FPGA

    Hi, I have a Zybo board and am using Vivado 2017.2. I have successfully written a number of VHDL modules allowing me to access the boards push-buttons, LEDs and slide switches using only the PL part of the device. I wondered if it was all possible to drive the LD_MIO LED from the FPGA? From my understanding it should be possible using the EMIO but have not been able to find an example or tutorial that shows how it is done. Regards FarmerJo
  2. Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  3. I have a ZYBO Board working fine with linux3.18. I have tested UART, I2C and Ethernet using linux3.18. But I needed to update my linux to 4.9, now ethernet cannot be configured. when I give ifcofig -a lo Link encap:Local Loopback LOOPBACK MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) It lists lo and sit0 and no eth0. I have searched web for a solution, but could not get anything useful. an someone help?
  4. Hi, I have 2 elf files, one for ps_cortex_a9_0 and another for ps_cortex_a9_1. How do I flash the 2 elf files together on zybo using fsbl? (Since it allows only one bootloader to be flashed at a time). Also, before that how do I run both elf files together? Both are simple bare metal applications. Basically hello world with even indices is being printed on 1 cpu and with odd indices is being printed on the other. I'm able to verify each application separately but I do not know how to run both together?
  5. Zybo Zynq Guitar effects

    Hello, I recently purchased a Zybo Zynq 7000 development board and would like to implement some modulating guitar effects like chorus, phasing, and flanging with the FPGA and was wondering if anyone has had any experience in this area.
  6. I am fighting to get any one of 5 different simple ZYBO demos to work. At all. I can download bitfiles with my own Verilog code and blink, or scan, or pulsate the LEDs, and get behaviour changes based on buttons and switches ... so I know the board works, but nothing I do with the with the processor core (PS block) works. I am here looking for information on how to get some kind of information out of the board so I can figure out what's going on. The demo I am working on now is this one: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start It does not ask for a Debug Configuration, or a Run Configuration, ... just the Run as -> Launch on hardware. There is a terminal setup at the end of that tutorial. Frankly I don't know why a separate console is needed since SDK has a "Console" and an "SDK Terminal". Nonetheless, I tried 'screen' and putty as others recommended, then minicom as well ... all I ever see is a blank screen. I don't know what I should expect to see really. I followed the tutorial to the letter. The only indication I get that things are connected at all is that with screen and putty, when I hit any key, I see ZYBO's TX LED flash once. I am running Ubuntu 16.04 and Vivado 2016.4. I have lots of Xilinx experience, but all command line and not with SDK (so telling me "It's just like ISE but ..." will make me cry. I just want something out of the console. Smoke would be nice. If it helps, I do see this in XSCT Console: Downloading Program -- /-----/projects/zybo/ZYBO_getting_started/ZYBO_getting_started.sdk/getting_started_with_ZYBO2/Debug/getting_started_with_ZYBO2.elf section, .text: 0x00100000 - 0x00102467 section, .init: 0x00102468 - 0x0010247f section, .fini: 0x00102480 - 0x00102497 section, .rodata: 0x00102498 - 0x0010263b section, .data: 0x00102640 - 0x00102adb section, .eh_frame: 0x00102adc - 0x00102adf section, .mmu_tbl: 0x00104000 - 0x00107fff section, .init_array: 0x00108000 - 0x00108003 section, .fini_array: 0x00108004 - 0x00108007 section, .bss: 0x00108008 - 0x00108037 section, .heap: 0x00108038 - 0x0010a03f section, .stack: 0x0010a040 - 0x0010d83f 100% 0MB 0.5MB/s 00:00 Setting PC to Program Start Address 0x00100000 Successfully downloaded /-----/projects/zybo/ZYBO_getting_started/ZYBO_getting_started.sdk/getting_started_with_ZYBO2/Debug/getting_started_with_ZYBO2.elf Info: ARM Cortex-A9 MPCore #0 (target 2) Running So it's "running", there is no debug config, and the Hello World demo says I should see: > The demo will be running on the ZYBO. Try playing around with the 4 switches (labeled SW0-SW3). Doing so should light its respective LED. Also over the serial port, pressing each button (labeled BTN0-BTN3) will produce the message “button x pressed”. Any suggestions appreciated. What do I do? Create a debug config for this and try again? GogMagog
  7. Still no terminal messages from Zybo

    I started this post and got a good response. I was able to use jpeyron's project (Hi Jon) to get the Zybo Getting Started to turn on LEDs with the switches. However, I still cannot get any output on any console. I am sticking with his project until I get this console business sorted out. Here's what I have: Vivado 2016.4 on a 64-bit Ubuntu 16.04. I'm trying this: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start and I do indeed have the correct board activity (LEDs and switches). On power on, I see this: abc@Kassandra:~$ lr /dev/ttyU* ls: cannot access '/dev/ttyU*': No such file or directory turn on the Zybo and: abc@Kassandra:~$ lr /dev/ttyU* crw-rw---- 1 root dialout 188, 1 Sep 14 18:08 /dev/ttyUSB1 So it looks like it's ttyUSB1. I am in the dialout group. I have tried, minicom, screen, putty, and cutecom, all with /dev/ttyUSB1, 115200, 8, none, 1, and I've played around with the flow control. If I type anything in the console I see the Zybo board's TX led flash. So it's the right port and I can program the board, and the SW is running on the Zynq. But I never get anything out on the console. The "getting started" is meant to tell me via the console which button I pushed (and that's something I so want to know). I have read and tried about 20 different "solutions". Any help appreciated as I have had zero success. Specific question: For anyone else with Vivado 2016.4 on a 64-bit Ubuntu 16.04, have you had to install the Digilent Adept SW to get this working? Any help appreciated as I have had zero success and for the first time in my many years I'm thinking about Altera. GogMagog
  8. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  9. Hi, Is there a good example to establish communication between Zynq and Microblaze processor on Zybo? I am looking to understand how to get both these processors to talk to each other, share data etc. I'm aware of this Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp1093-amp-bare-metal-microblaze.pdf But i'm looking for something simpler and on Zybo. Thanks.
  10. Zybo and UVC(USB Video Class)

    Hello, everyone! I am now working on a project which have an action cam connected to HDMI Input and then filtered with HLS Video Library and then i wanted to use the Zybo as a generic webcam to the pc host. What I wanted to ask is how do I configure my UVC linux kernel so that it receives the video output from my PL that I connect to my PS through AXI Mem Interconnect, and then ready to use as USB Webcam? Also, can I run an OpenCV apps which generated from Vivado SDSoC and output the video to the uvc? Any helps and hints appreciated, Thanks!
  11. Zybo webserver

    Dear, At the moment me and and a few friends are testing different IOT's. To upload data from a microcontroller or fpga to a webserver. Or upload to our website with $ comments. So our website will place the value's in the webserver. Now our question is. How can we connect our zybo board to the internet. We know we need to use the ethernet port but its very hard to find any information about uploading data with the zybo board. We use the zybo board with the vivado 2016 version. Greetings, Niels
  12. I am trying to boot embedded linux on Zynq Zybo with reference to this document: http://80.93.56.75/pdf/0/7/6/4/8/07648722.pdf I have created boot.bin(containing FSBL.elf, my custom hardware bit file and u-boot.elf) devicetree.dtb, uimage and uramdisk.img.gz in ZYBO_BOOT in sdcard as given. When I tried to boot Zybo inserting SD card in the board, nothing shows in the hyperterminal. Instead of my custom hardware, I have created a boot.bin file from the ZYBO Base System Design (available on the ZYBO product page of the Digilent website). Now it responded but showed the following error in the hyperterminal: MAC Addr: D8 80 39 5C F9 FC No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d initcall sequence 04062bf8 failed at call 04046944 (err=-1) ERROR ### Please RESET the board I think the error is from the u-boot-digilent/lib/fdtdec.c when CONFIG_SPL_BUILD is not defined. But the reason for not defining it is not known! What would be the reason?
  13. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: https://reference.digilentinc.com/reference/pmod/pmodsf/start ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  14. Least PL logic intensive data gathering

    Dear all, I hated the fact the Zybo Zynq does not have a proper D/A converter on its own. So I programmed a VHDL 1-bit delta sigma modulator according to this Link. The delta sigma modulator is working as a charm, but I want to be able to set the frequency of the waveforms i am generating. I want to set the frequency of the waveform by using an 1-10V input signal. I am okay with C and VHDL but I have never used the block designs or Zynq IP & GPIO Blocks.. The PMOD connector connected to the fpga is already in use so I guess my options are. Use a external microcontroller with ADC and use SPI to the PS part of the zybo zynq. Use the XADC connect it to the PS and of course use a voltage divider or something Microcontroller and just bit bang the values directly to the PL side Are there any suggestions on the easiest way of doing this ? ps: Is it possible to do something similar to interrupts in VHDL
  15. Hello, I just received my Zybo board, and I would like to use the DMA Audio demo to have audio input and output ready-to-run on my board. I chose to put the project into Vivado to be able to see the block design and make changes in the design later on. I did the following steps : - Downloaded the ZIP archive you can find on https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start - Created the project with TCL command and create_design.tcl file - Opened block design by adding the BD file as a design source in Vivado - Added the d_axi_i2s_audio_v2_0 IP to Vivado When I tried to synthesize, implement and generate the bitstream, I got an error saying : [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: C:/Users/Lucile/Zybo-DMA-3essai/Zybo-DMA/src/bd/design_1/design_1.bd Locked reason: * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: design_1_auto_pc_0 design_1_processing_system7_0_axi_periph_0 design_1_processing_system7_0_0 design_1_axi_mem_intercon_0 design_1_xlconstant_0_0 design_1_axi_iic_0_0 design_1_rst_processing_system7_0_100M_0 design_1_d_axi_i2s_audio_0_0 design_1_xbar_0 design_1_xbar_1 design_1_auto_us_0 design_1_auto_us_1 design_1_auto_pc_1 So I looked for some support and I followed https://www.xilinx.com/support/answers/63645.html, and in the design source the IPs look unlocked as said in the previous page, but I still get the same error. It also puts me this error : [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: [...same list...] I tried deleting each block and putting it back in the design, but it didn't change anything. Does someone have a solution for this ? It keeps me from generating the bitstream and exporting it to SDK. I also have several errors of placement, first I got this one : [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites. Term: ac_bclk I found out that the port ac_bclk was mapped to pin K18, but btns_4bits_tri_i[0] is also mapped to K18. Is it an error that others had with this demo ? To solve this I mapped ac_bclk to pin K14 which was free. I then got another error of the same type : [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: IIC_scl_o Term: IIC_scl_t Term: IIC_sda_o Term: and IIC_sda_t [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 6 | LVCMOS33(6) | | | +3.30 | YES | | | 35 | 50 | 7 | LVCMOS33(7) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 13 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | IIC_scl_i | LVCMOS33 | IOB_X0Y24 | N18 | | | | IIC_sda_i | LVCMOS33 | IOB_X0Y4 | N17 | | | | ac_mclk | LVCMOS33 | IOB_X0Y0 | T19 | | | | ac_muten[0] | LVCMOS33 | IOB_X0Y3 | P18 | | | | btns_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y1 | P16 | | | | btns_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y36 | Y16 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | ac_bclk | LVCMOS33 | IOB_X0Y60 | K14 | | | | ac_pbdat | LVCMOS33 | IOB_X0Y84 | M17 | | | | ac_pblrc | LVCMOS33 | IOB_X0Y77 | L17 | | | | ac_recdat | LVCMOS33 | IOB_X0Y76 | K17 | | | | ac_reclrc | LVCMOS33 | IOB_X0Y83 | M18 | | | | btns_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y75 | K18 | | | | btns_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y80 | K19 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ We can see that ac_bclk has been mapped to K14 which is what I wanted but why do I still get the previous error about ac_bclk ? And also where should I map those 4 new ports ? Is it normal to have that many errors on a demo which should work without any modification ? Any help would be greatly appreciated ! Regards, Lucile
  16. Audio processing on Zybo with DMA Audio Demo

    Hi, I recently purchased a Zybo board and used the DMA Audio Demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start) to acquire audio input and output. The Audio codec records 5 seconds of audio and then passes it to the Zynq PL via I²S protocol, that is it transmits the bit clock BCLK, the word select RECLRC and the data recorded RECDAT. My goal is to take this data and apply a filter on it, before the stream is mapped into memory with a DMA and then sent back to the audio codec and played in earphones. But I don't really understand how the data is received by the PL and where to find it (in some buffer I guess) in order to take it, process it, and then put it back in a different buffer where the DMA could access it and do his thing. Does anyone have experience with this demo that could help me figure this out ? Thanks, Lucile
  17. XADC PS side, zybo zynq

    Dear All, For the first time im trying to get the XMOD working with the PS side and print the values in a terminal. I tried a bunch of tutorials like the microzed chronicles.. I ended up using the tutorial posted as attachment, as attechments I also included my sourcecode and block design. I tried debugging by making several prints and I know the code works untll at least the "Test2" printf. During the build, no errors or anything appear. So i'm a bit confused into finding out where it all goed wrong. xadc.pdf design_1.pdf lab3.pdf
  18. Using Zybo Audio Codec W/base Design

    Hi all, I'm trying to get something working with the audio codec on the Zybo board. In the end, I want to sample an electronic musical instrument, do some signal processing, and output the processed signal, but for now I'm trying to get the demo from the base design working. I can get the demo to work using the supplied bit stream by creating an SDK project with the bitstream provided in the project files. If I open the PL project in a newer version of Vivado (2014.3), upgrade the IP cores, generate a bitstream, and run the demo from the SDK as before, the program hangs and doesn't print anything to the terminal. I've narrowed down where the program hangs using print statements to when the audio codec is being initialized. In particular, it seems that the code has an issue with the "Xil_Out32()" around line number 146 of the audio_demo.c file. To me this likely means that there is an issue with the programmable logic, so perhaps when I upgraded the IP cores for the new version of VIvado? I've also tried deleting the generic IP cores in the block design and running the connection automation, but with the same results. I am using an external supply to power the board with 5V and a max of 1A, so that shouldn't be an issue. I'm curious if anybody else has tackled something like this and/or updated the Zybo base design for newer versions of Vivado. -J
  19. Running XAPP1079 on Zybo

    Hi, I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that? Below are the tcl scripts that i have modified. I have tried running the profile both on the 2017.1 and the 2015.4 version of Vivado. It is possible that it has something to do with the standalone bsp. I have tried running a simple hello world from a single core of the ARM A9 and it runs just fine. But when I try running a simple hello world application with both the cores (essentially changing the SDK part of the XAPP), I still see nothing on the terminal.
  20. Hi, I am new at this area. My current project required to know the use of HDMI and VGA port of Zybo board. As a starting point I got a sample demo project(https://github.com/Digilent/Zybo-hdmi-in) by digilent but that was done in Vivado 2016.4. I am working on Vivado 2017.2 windows PC. I successfully convert that project in current version and able to generate Bit stream successfully. The problem is when I lunch SDK, it gives me errors. Can anyone help me? Or can anyone gives me some simple project which from where I can get idea about how to use HDMI and VGA port? Thanks.
  21. Splash Screen in u-boot

    Hello! I've been experimenting with embedded linux on zybo and after discovering https://github.com/Digilent/petalinux-bsps I managed to boot linux on zybo with hdmi output. But is there a way to attach video driver in u-boot in order to display splash screen (hdmi)? What would be the way to go about it?
  22. Zybo Echo Server not working

    Hi, In the SDK I have created the lwIP echo server project which builds OK. I have connected the Zybo to my laptop which has an IP address of 192.168.1.1 and subnet 255.255.255.0. Without using telnet or putty initially the terminal output is as follows. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back Start PHY autonegotiation Waiting for PHY to complete autonegotiation. Auto negotiation error Phy setup error Assert due to phy setup failure I have also tried to connect using putty before this timeout occurs but still unable to get echo functionality. I have checked in my Vivado project and can see that ENET0 is enabled and ENET1 is disabled. Is this correct? The project README.txt file mentions a couple of assumptions that it makes. That a timer interrupt is connected to the interrupt controller and that all ethernet peripherals accessible from the processor can be used with lwIP. How do I verify that these two requirements have been met? Other than that, any ideas why this does not work? (I have an ultrazed-eg board and the echo server works OK for that). Regards FarmerJo
  23. For the past 3 weeks i have been fiddling around a bit with zybo even though i have just found out about what an fpga is using vivado i have made some simple projects like a full adder using vhdl source code and hardware manager, an AXI IP block that can output PWM for given DUTY and Frequency/Period input. But now i have hit a stand still in my new IP design, i need two counters that run simultaneously one will be a clock running at 50Mhz and the other will be catching the input signal the block gets and counting it. My main problem is if i put both counters in the same process are they still as sensitive, and if they are not how can i trigger the other counter without getting a Multi-driven net error when one reaches the limit i want if they aren't in the same process(like one counter counts as a clock and gives me the info about the other clock in 10 ms intervals, in a way an encoder would.)
  24. Hello, I would like to know if the PL in Zybo boards can be used for a HDL FPGA design without the Zynq PS (no software). Is there some reference/demo/example about this case? Particularly, I want to know how to connect the USB-UART port to a custom HDL (UART) Module in the PL section, but using the same pins (i.e. MIO48, MIO49) that Zynq normally uses. Thanks in advance
  25. PmodRS485 on Zybo

    For various reasons I need to use RS485 for communication with my Zybo board. PmodRS485 seems to be a perfect add-on module, however, so far I could find only an MPIDE example. In my understanding Xilinx Uart should be the way to go because the Analog Devices chip is supposed to take care of the protocol. Correct me if I am wrong. Hope someone has such experience and can share it with us. Thank you!