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Found 27 results

  1. Hi. I've tried to operate Pcam-5c at Zybo-Z7-zynq7020 using Xilinx Vivado tool. I refered to source code for Pcam-5c posted on github( ). It operated successfully but I want to try again using other camera module instead of Pcam-5c. I have some problems in MIPI formatting data because Zybo7020 & Pcam-5c use RAW10 data but my camera module use RAW12 data. How can I use RAW12 format with Zybo-Z7-20 ?
  2. Hi, I have noticed an issue in a bare-metal application when polling the register XUARTPS_ISR (Channel Interrupt Status Register). No issues when I use XUART_SR (Channel Status Register) instead. The issue: When I poll XUART_ISR for TX_FULL and RX_EMPTY the UART interface becomes an unstable state. No sending and receiving after a few bytes is possible. Has somebody noticed the same issue or can somebody explain whats happening? Edit: My current code for the UART interface (Here I use XUARTPS_SR instead. But when I poll XUARTPS_ISR (0x14) it doesn't work.): #include <string.h> #include <dev/io.h> #define UART0_BASE 0xE0000000 #define UART1_BASE 0xE0001000 #define UART_CR_OFFSET 0x0 #define UART_CR_RXRST 0 #define UART_CR_TXRST 1 #define UART_CR_RXEN 2 #define UART_CR_RXDIS 3 #define UART_CR_TXEN 4 #define UART_CR_TXDIS 5 #define UART_MR_OFFSET 0x4 #define UART_IER_OFFSET 0x8 #define UART_BGEN_OFFSET 0x18 #define UART_SR_OFFSET 0x2C #define UART_SR_RXEMPT 1 #define UART_SR_RXFULL 2 #define UART_SR_TXEMPT 3 #define UART_SR_TXFULL 4 #define UART_FIFO_OFFSET 0x30 #define UART_BDIV_OFFSET 0x34 struct uart_reg { unsigned int cr; unsigned int mr; unsigned int ier; unsigned int bgen; unsigned int sr; unsigned int fifo; unsigned int bdiv; }; static struct uart_reg regs; void uart_init(void) { unsigned int tmp; = (UART1_BASE + UART_CR_OFFSET); = (UART1_BASE + UART_MR_OFFSET); regs.ier = (UART1_BASE + UART_IER_OFFSET); regs.bgen = (UART1_BASE + UART_BGEN_OFFSET); = (UART1_BASE + UART_SR_OFFSET); regs.fifo = (UART1_BASE + UART_FIFO_OFFSET); regs.bdiv = (UART1_BASE + UART_BDIV_OFFSET); /* Check if RX/TX is enabled */ tmp = io_rd32(; /* Skip init if RX/TX enabled */ if (tmp & ((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN))) return; /* Reset RX/TX paths */ tmp = io_rd32(; tmp |= ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST)); io_wr32(, tmp); do tmp = io_rd32(; while (tmp & ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST))); /* Set baudrate to 115200; UART Reference Clock: 100MHz */ io_wr32(regs.bgen, 124); io_wr32(regs.bdiv, 6); /* Set mode: 8 Databit, 1 Stopbit, No Parity */ io_wr32(, 0x20); /* Enable RX/TX */ tmp = io_rd32(; tmp &= ~((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN)); io_wr32(, tmp); } int uart_send(unsigned char *buf, int len) { int i; unsigned int tmp; for (i = 0; i < len; i++) { do tmp = io_rd32(; while (tmp & (1 << UART_SR_TXFULL)); io_wr08(regs.fifo, buf[i]); } return len; } int uart_recv(unsigned char *buf, int len) { int i; int ret = 0; unsigned int tmp; tmp = io_rd32(; if (tmp & (1 << UART_SR_RXEMPT)) return 0; for (i = 0; i < len; i++) { buf[i] = io_rd08(regs.fifo); ret++; tmp = io_rd32(; if (tmp & (1 << UART_SR_RXEMPT)) return ret; } return ret; }
  3. Hi. I have a problem while trying lwIP Echo server wiht Zybo-Z7 I follow this tutorial faithfully but I face with a problem This problem occurs for both connection through router and connection directly with my laptop or desktop I try with 3 PC and all of it shows same result. Google suggest me to configure ethernet to be 100Mbps half duplex with Fixed IP settings and it doesn't work. I double-check that I'm using correct MIO pin and fix the 100Mbps at SDK. Is there any solution to resolve this problem? Thank you.
  4. in the Zybo-Z7 P-CAM 5c Demo that is from , it uses axi video stream which only contain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast in my case i want to make a video processing using vivado hls after making the IP block of my vidio processing the ip generated with ontain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast axis_vidoe_tstrb axis_video_tdst axis_video_tkeep axis_video_tid after making the ip and conneting to zybo Z7 Pcam 5c demo i couldn't see the output of the camera anymore hopefully any one can help my problem to match or create an axi video stream in vivado hls for project zybo-z7 Pcam 5c demo
  5. Hello, I'm new to this form, looking for some help with the Dual H bridge PMOD DHB1. I connected my power supplier to J4, my motors to J5 and J6. I have a custom IP that uses switches to drive motor speed with most significant bits of a duty cycle for PWM output at 2kz. I also have 2 switches connected to the DIR1 and DIR2 respectively. I also have button 3 connected to a reset condition to initialize code, inputs and outputs. To help debug, I connected the EN1 and EN2 output of the custom IP to the board LEDs to confirm that the signals are working correctly. I also checked the voltage at EN1 and appears to be doing what I expect. However, I do not have any motor actuation. I checked the voltage at the J4 = 8V, but neither J5 or J6 have any voltage differential between M+ and M-. I checked the sleep and fault pins they are both high, which is normal behavior as they are pulled low when in sleep or faulted state. Any advice on what I can do to find an issue would be appreciated. Thanks, Dave HBridgeTOP Hbridgecode (1)
  6. I am newbie with ZYBO Z7-20 working on hdmi in demo , i have done as shown on github digilent project page in VIVADO 2019.1 , But unable to get the video output ,but my system detecting the Board as DGL 720P CEA and UART port shows HDMI UNPLUGGED i have tried hdmi pass through , My system is not detecting the display itself i see video capture .state is video disconned in VIdeoinitilaztion it not changed any where ..and video_start function wont work Please Help ... Whether i have to change vivado version or any code
  7. Hello, I'm working with the Zybo Pcam 5C (18.2) reference design. While using the default resolution of 1920 * 1080 - I observe the AXI Stream but exiting from the GAMA CORRECTION IP (this is last core in the video chain before the VDMA). A strange thing I noticed is that the first 4 lines at the beginning of each frame are a constant 0xAE for all pixels. ( all the red , green and blue pixels have the same value which is 0xAE ). After the first 1920 * 4 pixels non - constant data starts to arrive. Why is this ? Is this the way the sensor outputs data ?
  8. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design ( with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  9. Hello, I have been trying for a while to run this PCAM example that is provided by Digilent on a Zybo z7-10 board: After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any video output from it. All I get is a static noise pattern, despite of trying to pick different options from the C++ menus. I am able to see the resolution change and read out the camera's registers (which seem to be correctly set according to the libraries), but that's it. What could I possibly be doing incorrectly? I see the same pattern on a different monitor and have previously tested the hdmi output from the board both through plain VHDL and the IP integrator, via the test pattern generator. I do not see any errors apart from the negative slacks in Vivado, which is a known issue..
  10. Hello, We are trying to generate the SPI protocols signals from the Zybo-Z710 board, which uses Zynq-7000 SoC. Since, the PS section of the chip contains two SPI modules. Can anyone tells me the procedure for activating the SPI line inside the PS. I want to use this SPI lines to transfer data and provide control to the another module. Thanks AMOL
  11. I have implemented a small system with ZYBO-Z7 20 , It will send the switch status through Ethernet interface . Implemented with AXI GPIO and LWIP ,UNICAST ,BOARD HAS CONSTANT IP and REMOTE IP is CONSTANT. i am not using DNS I am able to Send packets if Board is connected directly to LAPTOP and i am able to PING the Board from LAPTOP But when the Same setup when connected to Switch [allied telesis] i am not able ping the board and no packets are flowing ... Can any one help me where i have to look...
  12. Hello, I am working on the Zybo-Z7-10 development board, I want to establish a web server application to upload files from my PC and send it to web browser by HTTP POST and extract data inside the file, I am using the lwIP stack and downloaded the xapp1026 files from the gitHub, right now I can run the example application correctly, but I want to change the content inside the image.mfs file provided by the xilinx, I cannot open it, once I open the image.mfs by NotePad, unreadable characters are displayed, I found that at the top of this file, there is a css part, on the bottom of this file I can recognize that there is a html part, so I have modified it by adding a part of <input type= "file".....> , however it is vulnerable to errors, besides, i still need to write the js functions for getting the file. Do you know how can I create my own web browser and do not use the image.mfs file? Actually, I tried the mfsgen -cvbf command too, but I cannot change anything inside the file! can you help me on this problem or provide me with some references for the same question? Thanks a lot!
  13. Trying to get started with the Zybo-Z7 board and following the "Getting Started with Zynq" tutorial ( here ). Using Vivado 2018.2 because that's what the latest Pcam tutorial uses (my ultimate application). I can get down to the point where you add the 2 gpio IP blocks. But when "Run Connection Automation" is selected, the popup window does not have an option to select the board interface (switches and LEDs). These are un-commented in the constraint file. I'm using the latest board files and constraint files. Project Summary shows the correct board part. I have a feeling I'm missing something simple. I've uninstalled/reinstalled everything. It's a fairly new W10 computer. I've looked at several other getting started type tutorials and no clues there. I've done embedded systems before so not a complete novice, but i feel like one right now...
  14. Can anyone suggest me how to program the UART/USB available in the ZYBO Z7 board and use it as a port to feed the data from the PC/SERVER ?
  15. Hi, I'm looking to run the Zybo Z7-10 HLS Video Processing Workshop as part of a Road Test for element14 as well as for a Robotic project I have but I am unable to access the site for the Workshop. When I click on the link at the bottom of the Zybo Z7 reference site, I get a status of Site is offline and the following error: "Database connection error (code #0)" Also, I had see the following link listed in another forum post as well in a element14 Webinar but it errors out as well. This produces the following error: "Error establishing a database connection" Is the Zybo Z7-10 HLS Video Processing Workshop still available or has it been replaced by something else? I did find the following GitHub repo for the Zybo-Z7-20 and Pcam-5c which is what I am looking for but I am not sure if this will work with the Zybo-Z7-10. Cheers, Jon
  16. hayesjaj

    Zybo-z7-10 Step File

    Are the step files available for the Zybo-z7? I could not find mechanical drawings anywhere in the resources section or on github. I would like to 3D print up an enclosure for it.
  17. Sduru

    AXI4 and Vivado ILA

    Hello, My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals. Many thanks...
  18. Hi, I have been looking for a complete documentation reguarding the zybo z7-20 board but without any success. I need a documentation where i can see also how to set up the I/O in the XDC constraints file. Will be very helpful if you could drop me the link. Also, when i turn the board off and restart it, it reset itself to factory default and i can't really program it permanently, i tried to program it in the three different modality and also entered the memory info but then i do not know what file to upload in the configuration memory device. Thank you
  19. Hello, I am using Vivado 2018.2 i downloaded "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project in original project "part" option is choosen then I created a new vivado project i choose "board" option and i created same block design with "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project. I inserted same IP blocks and made connections. I did synthesis and implementation succesfully but when i exported to SDK and i tried to boot from SD card (i used hello world template) i did not see anything on terminal but when i am trying to export original project to SDK not which i create, then i can see hello world message on Terminal. Why did i not see anything in my project but i saw in original demo project? what could possibly be the problem? Hoping to read from you soon Best regards
  20. Hello Digilent Community, I am working on a image processing project and was wondering if anyone had advice or could point me in the right direction. I have tried following some tutorials and example projects, but I am still trying to wrap my head around Xilinx Vivado and SDK. The project really shouldn't be very difficult, I think I am just missing some information or the best way to go about doing it. For the project I am using the Zybo z7-20 development board and want to save two images to an SD card. The two pictures are black and white frames from a video just seconds apart, so there is only slight change in the frames themselves. I want to compare the two frames and output either a black and white image of the change in pixels or a binary file of '0' being an unchanged pixel and '1' being a change in the pixel. MATLAB has the 'Computer Vision System Toolbox' 'Tracking Cars Using Foreground Detection' Simulink example that is similar to what I want to do on the Zybo z7-20 FPGA. The following figure show the original video (right) with blob detection (the green square) and the binary output image of the change in pixels in the foreground (left). I want to use the Zynq Processor and write C code to do the analysis, but I haven't found a clear way to access the SD card from the Xilinx SDK. The following figure is of my current Block Design with only the Zynq Processor as well as some GPIO to test. I am still researching and looking at examples to compare, but wanted to see if the community had any pointers or if someone has done this before. I am a college student and I have been really interested FPGA's and digital design for the past 6-9 months, but I have mainly written my own Verilog code and haven't worked with block design or running C code on any of my designs. Any comments or suggestions would be great. Thanks!
  21. Hello, I've been to set up a new Zybo board but I'm stuck with a serial port issue. I built my design with the provided board files in Vivado 2017.4. I tried a simple "hello world" in SDK but only got a bunch of unprintable characters. I have Tera Term set up for 115200, 8-bit, 1 stop, no parity. I tried Putty as well and had the same results. I verified the Vivado project is using UART1 MIO48..49. I intermittently can get the correct initialization message from the preloaded QSPI image, but most times it's unprintable characters. I also tried the pre-built Linux from the 2017.4 Zybo Petalinux BSP with the same result. It's definitely booting, but the terminal output is unprintable characters. Other things to note: * I'm running off USB power. I'm plugged directly into my laptop * Sometimes pressing the Reset button makes the PGOOD LED flicker until power cycled Thank you Richard
  22. Hi, I've started using the platform for SDSoC on Zybo-Z7 from I tried creating a linux based "Hello World" application and was able to successfully run it on the board. I would like to start using GPIO and other peripherals for simple image processing application. When I add #include "xgpio.h" in my main.c file and build (found an online YouTube video demonstration), SDSoC is not able to locate the xgpio.h file. Is there a solution to this? I don't get any error when I choose freeRTOS instead of linux. Thank you!
  23. I've read the Reference Manual for ZyboZ7,it shows the Memory Part of ZyboZ7 is "MT41K256M16HA-125 DDR3L",but when I create a "helloworld" project in Vivado 2018.2,I did not see it at the list. So should I do something to add the suitable memory part in Vivado,or select someone to replace it? I've tried some memory parts,but they all failed,there was nothing displayed in the terminal.
  24. Hi I am trying to run the fsbl and hello world on Zybo-z7-10, but seems like it does not work. When I tried to run the fsbl, it shows the message like this. I build this project step by step learning from a video on youtube, the hardware and software part. I post this link at the bottom. The output in terminal is supposed like this, tell me Boot mode is JTAG, but now it is not. Does anyone know why this happen? If FSBL does not run successfully, the other parts in my project won't work as well since the the clock and interrupts from PS side are not activated. For example, in EnableSampleGenerator, I assign 32 and 1 to GPIO, but when I read from it, they are still 0. Also after I start first DMA transmission, when it finishes, there should be an interrupt, and in the interrupt I start another DMA transmission. Now seems like the interrupt never happens, so I seriously doubt the FSBL does not run properly. Thanks a lot in int main()
  25. hello, can I change the reference clock for Dynamic Clock Generator IP core? Which frequency do I have to provide for REF_CLK_I?