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Found 471 results

  1. hey there I am a beginner to zynq. I have bought a zybo board. I am using vivado version 2015.4. I followed the below link to add zybo board file to vivado: https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 then I this tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start?redirect=1 but it did not work. in this tutorial says: but when I select Hello world demo, I see the below attached image. it says that could you please tell me what I should do? thanks in advance.
  2. Hello All, I am having an issue with running the Master Polled example on I2C with the zynq. I have a base design that is set up and runs the self test and repeated start examples and completes them. My issue is that I hooked up an I2C sensor, added pullup resistors, and it is failing. The only thing I have changed in SDK is that I have found the address of my I2C sensor, 0x57, and put it in place of 0x55. I can place my block design and what not here for referencing. Update - I have assigned I2C pins to W19 and W20 to SCL and SDA respectively.
  3. Hi I want to utilize sdk to test echo server lwip,fpga program and run configration are done.However,in console,there are some lines make me confused. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back link speed: 1000 DHCP Timeout Configuring default IP of 192.168.1.10 Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 When I ping the board on PC,it displays "can't access the destination host" My board is Zybo.The hardware been built in vivado 2014.3.1 is a Zynq7 System Processing Core.What makes wrongs? Regards, Sophia
  4. I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me. Any help would be appreciated. This is the 3rd or 4th tutorial/example I have tried since getting the board today. All in all everything has gone smoothly up to this point, but I have not the fpga/vivado experience to determine the issue. also my log output from vivado is attached. implementation.txt
  5. Analogue Discovery 2 https://forum.digilentinc.com/applications/core/interface/file/attachment.php?id=12669 https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Ls1SAE&l=en-US Hi Firstly I would like to say what great product the Analogue Discovery 2 is, I have used it for 8 months to develop a product. It is by far the best PC scope that , I have used. Far better than a PICOSCOPE from the UK company PICOSCOPE or any of the Chinese PC scope knock offs. Analogue Discovery 2 is a serious peice of professional kit and not a toy. This a summary of all of the useful information I found when working with the Analogue Discovery 2 for 8 months 1. Always use the latest WaveformsSDK https://forum.digilentinc.com/topic/8908-waveforms-beta-download/ 2. vb.net driver rapper https://forum.digilentinc.com/applications/core/interface/file/attachment.php?id=9726 https://forum.digilentinc.com/topic/17736-digilent-analog-discovery-2-dll-driver-for-vbnet-and-c-in-visual-studio-2017/#comment-45135 3. C# complete .net rapper than can be used for vb.net as well as C# https://github.com/Andrei-Errapart/WaveFormsSDK It is possible to take full control of the Analogue discovery 2 using C# or vb.net or python or labview. 4. C# oscilloscope GUI panel that works and can be used in both VB.net and C# https://www.codeproject.com/Articles/16350/High-Speed-Feature-Rich-and-Easy-To-Use-Graphs-and I have tested this C# plugin and it works really well . 5. KICAD PCB tool projects that are very intersting This way you can make your own projects which plug onto the analog discovery 2 https://github.com/jubeormk1/AnalogDiscovery_x20_powerMainsProbe https://github.com/jamescarruthers/analogdiscovery2io https://github.com/james-everitt/AnalogDiscovery2Eurorack https://reference.digilentinc.com/_media/reference/instrumentation/analog_discovery_impedance_analyzer_sch.pdf 6. General https://github.com/Elektrolab/AnalogDiscoveryScope https://github.com/AndrewQM/AnalogDiscoveryScripts https://github.com/bienata/AnalogDiscovery2 https://github.com/pascalhuerst/FreqResp https://github.com/HutzlerLab/AnalogDiscovery https://github.com/holla2040/ad2 https://github.com/ATPanetta18/ADAP https://github.com/michael-christen/digilent_interface <<<<-- linux command line interfasce for AD2 The question ============= Will the waveforms SDK every be compiled to work on the Windows10 ARM64 platfrom. ?? see https://www.altomdata.dk/guide-koer-komplet-windows-10-paa-raspberry-pi
  6. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design (https://github.com/Digilent/Zybo-Z7-20-base-linux) with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  7. rcjhy8

    Zybo External LED Control

    Hi all, New to the FPGA world as I was tasked a project to help familiarize myself with the programming and function of how FPGAs work. As you can all infer, I am in need of some help on a specific project that I am doing. I am using a ZYBO Zynq 7000 development board, and Vivado 2019.1. What I am trying to do is control an external sensor, or LED through some user interface. I have seen a lot of tutorials that use the on-board LEDs, and if you press a button, it displays that value in binary in a command terminal. My task that I was to do is be able to turn on and off an external LED connected to the ZYBO through the command terminal. It seems I can connect a simple circuit with a LED and a resistor to the PMOD pins that are power and ground. What the command terminal would let me do is then essentially cut power to that pin, therefore turning the LED off. Please let me know if this is probable, and/or how I should task to complete it. Thanks, Russell
  8. Hi everyone ! I'm working on the zybo board. There is a yocto linux on a SD card, and the system boot on the SD card. This works very well. Now I really enjoy if I could understand how to link vivado (to generate bitstream) and yocto ! I'm a little lost about this link. I read that some people say to use the layers meta-xilinx-tools ? Someone already use it ? I don't really understand how to use it, and how manage the boot.bin, u-boot, fsbl ... etc Could you help me please ? best regards, Yohan
  9. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  10. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. https://www.dgbwiki.com/index.php?title=FPGA_mining https://www.coinfoundry.org/pool/dgb5 DigiByteCoin Github Odocrypt Mining Software https://github.com/DigiByte-Core/odo-miner It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  11. Hi all, Currently I am working on a project with the aim to encrypt the communication between a drone and the ground station by using an PYNQ-Z1 board. I am facing the issue of how to convert the standalone application (bare metal) to a Linux base application in Vivado 2019.1 SDK, in order to make use of the crypto++ libray which requires the presence of an perating system to work. Does anyone know what to do to slove the issue? Thanks George
  12. Hello Everyone, I just want to know Is linux interview tough? My interview has been scheduled in next week. Can anyone provide me list of interview questions for linux profile as a fresher level. I have covered some most important topics like Linux, BASH and DOS, symbolic links, daemons and some more.
  13. Hello, I’m having problems with sending large amount of data from ZYBO to a computer. For example, when I tried to send image data (640x480) at the maximum baud rate, the computer didn’t receive all data. But when baud rate was set to 256000, all data were received. It seems like UART buffer is overflowing. How to solve this problem? Best regards, Toni
  14. Kampi

    XADC - AD7 sampled on AD14

    Hello, I have a Zybo Board (Version 1 Rev. and I have a strange Issue with my XADC which samples the input for the channel AD7 on the channel AD14. Please take a look at my setup. I want to use the differential Channelpair 7 and 15 (like in the Photo - upper row VIn and lower row ground from my voltage source). My software gives me the results for channel 14 and 15 and the value for channel 7 stays constant even when I increase or decrease the input voltage. Only channel 14 and 15 change her values. I expect that channel 14 stays constant and channel 7 change his value. Temperature: 46.1576 Degree Celsius Vcc INT: 0.9961 V Vref+: 1.25 V Vref-: 3.00 V Channel 7: 2351 Channel 14: 26032 Channel 15: 32767 My code looks like this #include "stdio.h" #include "xparameters.h" #include "xadcps.h" XAdcPs XAdc; XAdcPs_Config* ConfigPtr; int main() { ConfigPtr = XAdcPs_LookupConfig(XPAR_XADC_DEVICE_ID); if(ConfigPtr == NULL) { xil_printf("Invalid XADC configuration!"); return XST_FAILURE; } XAdcPs_CfgInitialize(&XAdc, ConfigPtr, ConfigPtr->BaseAddress); if(XAdcPs_SelfTest(&XAdc) != XST_SUCCESS) { xil_printf("Self test failed!"); return XST_FAILURE; } XAdcPs_Reset(&XAdc); XAdcPs_SetSeqChEnables(&XAdc, XADCPS_SEQ_CH_AUX07 | XADCPS_SEQ_CH_AUX14 | XADCPS_SEQ_CH_AUX15); XAdcPs_SetSequencerMode(&XAdc, XADCPS_SEQ_MODE_CONTINPASS); xil_printf("Start...\n\r"); while(1) { u32 Temp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_TEMP); printf("Temperature: %.4f Degree Celsius\n\r", XAdcPs_RawToTemperature(Temp)); u32 VCCInt = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VCCINT); printf("Vcc INT: %.4f V\n\r", XAdcPs_RawToVoltage(VCCInt)); u32 VREFp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFP); printf("Vref+: %.2f V\n\r", XAdcPs_RawToVoltage(VREFp)); u32 VREFn = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFN); printf("Vref-: %.2f V\n\r", XAdcPs_RawToVoltage(VREFn)); u32 Ch7 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MIN + 7); xil_printf("Channel 7: %lu\n\r", Ch7); u32 Ch14 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX - 1); xil_printf("Channel 14: %lu\n\r", Ch14); u32 Ch15 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX); xil_printf("Channel 15: %lu\n\r", Ch15); xil_printf("-------------\n\r"); for(u32 i = 0x00; i < 0xFFFFFF; i++); } return XST_SUCCESS; } With the following XDC file: ##Pmod Header JA (XADC) set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_p] set_property PACKAGE_PIN N16 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_p] So what is going wrong here?
  15. When running from Xilinx SDK (2018.3) I cannot get the trivial "Hello world output" from my Zybo Z7 board. However I do get the following messages: Connected to /dev/ttyUSB1 at 115200 Initializing... init:done Zybo Z7-20 Rev. B Demo Image This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working. The port was initially not accessible due permissions but I have worked around by changing them with chmod. I also added myself to dial group by s'udo adduser audrius dialout' . This has no effect. I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly. I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior. I tried to move the jumper JP5 between JTAG and QSP1. The "Demo image" message shows up in QSP1 position. In JTAG position, just nothing appears. I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7). I am using Ubuntu 16 (4.15.0-43-generic #46~16.04.1-Ubuntu SMP Fri Dec 7 13:31:08 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux) I attach SDK logs and synthesis logs. Board files I have downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip. After installing as described in https://reference.digilentinc.com/vivado/installing-vivado/start I was able to find and select the Zybo Z7 - 20 after restarting Vivado. While the board was initially powered by USB 3, I tried the 5 V wall adapter later, no changes. Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful. Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start. sdk.log synthesis.log
  16. birca123

    ZYBO Image Processing

    Hello, is there any image processing library that can be used for standalone applications on ZYBO? Thanks, Toni
  17. I'm trying to run the Zybo Z7 Pcam 5C Demo... i'm really new at this, the instructions say: ********************************************************** To generate the project: 1. Open Vivado 2017.4 2. In the tcl console, type "cd [this directory]/proj" and press enter. 3. Type "source ./create_project.tcl" and press enter to generate the block design for the project. To run the demo from SD card: 1. Copy bin/BOOT.bin to the root of your SD card. 2. Set the boot jumper on the Zybo Z7 to SD. 3. Insert the SD card into the Zybo Z7 and power it on. ************************************************** I'm using Vivado 2017.4 and i've copied the board_files to vivado software. After the point 3. (Type "source ./create_project.tcl") I get 7 warnings about some pins... am im doing something wrong here? I'm a newbie. Can you help me out to make the demos work, thanks in advance! ********************************************************************************************************* ## create_root_design "" WARNING: [BD 41-1306] The connection to interface pin /sw_gpio/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /rgb2dvi_0/aRst_n(rst) and /v_axi4s_vid_out_0/locked(undef) WARNING: [BD 41-1306] The connection to interface pin /blur_edge_detect_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /color_to_bw_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl WARNING: [BD 41-1306] The connection to interface pin /invert_0/ap_start is being overridden by the user. This pin will not be connected as a part of interface connection ap_ctrl Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/ui/bd_c954508f.ui> WARNING: [BD 41-721] Attempt to set value '50000000' on disabled parameter 'C_S_AXI_LITE_FREQ_HZ' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '200000000' on disabled parameter 'kRefClkFreqHz' of cell '/MIPI_D_PHY_RX_0' is ignored WARNING: [BD 41-721] Attempt to set value '100000000' on disabled parameter 'kRefClkFreqHz' of cell '/video_dynclk' is ignored INFO: [digilentinc.com:ip:axi_dynclk:1.1-17] /video_dynclkFREQ_HZ of 100000000 propagated into CONFIG.kRefClkFreqHz INFO: [digilentinc.com:ip:MIPI_CSI_2_RX:1.0-17] /MIPI_CSI_2_RX_0Verified that video_aclk frequency can handle RxByteClkHS frequency. AXI-Stream bandwidth 600000000 Pix/s >= PPI bandwidth 134400000.0 Pix/s INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 50000000 propagated into CONFIG.C_S_AXI_LITE_FREQ_HZ INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 200000000 propagated into CONFIG.kRefClkFreqHz INFO: [digilentinc.com:ip:MIPI_D_PHY_RX:1.0-17] /MIPI_D_PHY_RX_0FREQ_HZ of 84000000 propagated onto RxByteClkHS Wrote : <C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/system.bd> VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/synth/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/sim/system.vhd VHDL Output written to : C:/DesignVivado/Zybo_Z7_Embedded_Vision_Demo2/proj/bd/system/hdl/system_wrapper.vhd make_wrapper: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.461 ; gain = 79.957 # set sdk_dir $origin_dir/sdk # set hw_list [glob -nocomplain $sdk_dir/*hw_platform*] # if {[llength $hw_list] != 0} { # foreach hw_plat $hw_list { # file delete -force $hw_plat # } # } # set sdk_list [glob -nocomplain $sdk_dir/*] # set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"] # if {[llength $sdk_list] != 0} { # exec xsct -eval "setws -switch ../sdk; importproject ../sdk" # } update_compile_order -fileset sources_1
  18. birca123

    ZYBO HDMI-IN

    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, Toni Birka
  19. Hi, I am working on a project where i use four UART for an application, all four uart lines sends and receives approx. 20 bytes of characters and expects 20 bytes o character in every 16 milliseconds. And the data transfer will be continuous. NOTE : All four UARTs, are on PL side and controlled by PS of my zynq SoC.. NODE B : Zybo NODE A : Subsystem The UART communication is between NODE A and NODE B. NODE A sends data to NODE B, in turn NODE B should receive the data and reply with an acknowledgement. In this case NODE B is my Zybo Node A is another subsystem. So the data transmission is initiated by NODE A and the control is with NODE A. NODE A will Enable the data transmission for all four UARTs. Now the problem which i am facing is, when NODE A enables the transmission for any two of the UART lines the data transmission is smooth, the problem arises only when i enable the other two. Which means the zybo is not capable of attending to those interrupts which is simultaneously coming from NODE A through four UART lines. My data contains Start byte and Stop byte, Both Start and stop byte are same character. I will attach a my Interrupt handler for reference. **************NOTE************** UART IP on PL side : UART16550 Type of UART : Interrupt driven. Software used : Vivado 2018.3 and SDK Bare metal software. UART interrupt priority : equal priority for all four UARTs. ********************************** I am not very sure about how to use four UARTs efficiently with my Zybo . Please help me with the problem, any inputs from your side will be appreciated. The following is my UART interrupt handler. *************************************************************************** static void RW1RecvHandler(void *CallBackRef, unsigned int EventData) { int i, ch, RecvCount, index; RecvCount = EventData; // repeat this loop for all chars received, i.e., for all ReceivedCount i = 0; while (i < RecvCount) { ch = RW1_RecieveBuffer[i++]; // get the received char from the buffer if(RW1_Start_byte_flag == 1) { // Stop Byte Check for RW1 if (ch == 0xc0) { // Ignore one of the two successive start byte characters if (RW1_ReceivedCount > 1) { RW1_Start_byte_flag = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; RW1_Frame_complete_flag = 1; } } else { if ((index = RW1_ReceivedCount) < TEST_BUFFER_SIZE) { RW1_Buffer[index] = ch; RW1_ReceivedCount++; } else RW1_Start_byte_flag = 0; } } // Start Byte Check for RW1 else if (ch == 0xc0) { RW1_Start_byte_flag = 1; RW1_ReceivedCount = 0; RW1_Buffer[RW1_ReceivedCount++] = ch; // Note the cpu time when first character is received XTime_GetTime(&t_start_RW1); RW1_Frame_complete_flag = 0; } } if(RW1_Frame_complete_flag == 0) { // set up the buffer for next char in interrupt mode XUartNs550_Recv(&RW1, RW1_RecieveBuffer, 1); } } Thanks & Regards Ajeeth Kumar
  20. Hi all, This is a quick and dirty howto. This howto describes how to use I2C modules (onboard and through PMOD connector) under embedded Linux. I've chosen to build my own Linux distro based on Linux kernel source for MicroBlaze softcore and busybox project for the init RAM DISK. My board is the Nexys4 DDR board. If you respect the following requirements for the HW design compatible with Linux, you can use Petalinux too. HW Vivado requirements (according to Xilinx UG1144) design to boot Linux: MicroBlaze with MMU support by selecting either Linux with MMU or Low-end Linux with MMU configuration template in the MicroBlaze configuration wizard. External memory controller with at least 32 MB of memory. Dual channel timer with interrupt connected. UART with interrupt connected. Ethernet with interrupt connected. Note that all peripherals you use must be interrupt capable. For the UART peripheral, if you have not enabled interrupts, you have no Linux console outputs. For the Nexys4 DDR, you can follow this online tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start At this stage, for the Nexys4 DDR board, you can add the onboard i2C temperature sensor (ADT7420) that uses the AXI IIC IP block. I've added a second external temperature sensor (PMOD TMP3) connected to PMOD JA pins of the Nexys4 DDR board. I've chosen to connect SCL TMP3 pin to JA1 PMOD JA pin (C17 FPGA pin) and SDA MP3 pin to JA2 PMOD JA pin (D18 FPGA pin). You connect GND and 3V3 pins from PMOD JA connector to corresponding TMP3 pins. You have finally 4 pins to connect. You obtain the Vivado design shown below. Notice that both AXI IIC IP blocks have interrupts connected for Linux compatibility. For the TMP3 sensor, I have an external port named temp3_sensor. I've created a XDC file containing: set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { tmp3_sensor_scl_io }]; set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { tmp3_sensor_sda_io }]; You can see that: tmp3_sensor_scl_io signal is for SCL I2C signal. tmp3_sensor_sda_io signal is for SDA I2C signal Please respect notation: xxx external I2C port gives xxx_scl_io and xxx_sda_io signal names in the XDC file. Generate .bit file. Launch Vivado SDK tool, install the device tree plugin and generate Device Tree files. You can follow this link: https://numato.com/kb/neso-microblaze-linux-run-linux-neso-artix-7-fpga-module/ Copy the generated pl.dtsi file (under project_1/project_1.sdk/device_tree_bsp_0/ directory) into arch/microblaze/boot/dts/ Linux directory. Use the generated system-top.dts file (under project_1/project_1.sdk/device_tree_bsp_0/ directory) to create the xilinx.dts file into arch/microblaze/boot/dts/ Linux directory. Be carefull with stdout options in the xilinx.dts file if you want Linux output enabled. Mine is: /dts-v1/; /include/ "pl.dtsi" / { chosen { bootargs = "console=ttyUL0,9600"; linux,stdout-path = &axi_uartlite_0; stdout-path = &axi_uartlite_0; }; aliases { ethernet0 = &axi_ethernetlite_0; serial0 = &axi_uartlite_0; i2c0 = &axi_iic_0; i2c1 = &axi_iic_1; }; memory { device_type = "memory"; reg = <0x80000000 0x8000000>; }; }; &axi_ethernetlite_0 { local-mac-address = [00 0a 35 00 00 00]; }; Generate your init RAM Disk for root File sytem. I suppose that you can do this. Generate your Linux kernel. I suppose that you can do this: $ make ARCH=microblaze CROSS_COMPILE=microblazeel-xilinx-linux-gnu- simpleImage.xilinx -j 4 Program the FPGA device and download the simpleImage.xilinx file (kernel + init RAM Disk) under arch/microblaze/boot directory into RAM with the JTAG interface and finally execute. That's all folks! Ramdisk addr 0x00000000, Compiled-in FDT at c03ad4f8 Linux version 4.14.0-00493-gb68293ad2c93-dirty (kadionik@ipcchip) (gcc version 8 setup_cpuinfo: initialising setup_cpuinfo: Using full CPU PVR support wt_msr_noirq setup_memory: max_mapnr: 0x8000 setup_memory: min_low_pfn: 0x80000 setup_memory: max_low_pfn: 0x88000 setup_memory: max_pfn: 0x88000 Zone ranges: DMA [mem 0x0000000080000000-0x0000000087ffffff] Normal empty Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000080000000-0x0000000087ffffff] Initmem setup node 0 [mem 0x0000000080000000-0x0000000087ffffff] On node 0 totalpages: 32768 free_area_init_node: node 0, pgdat c0525af4, node_mem_map c07a2000 DMA zone: 256 pages used for memmap DMA zone: 0 pages reserved DMA zone: 32768 pages, LIFO batch:7 pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 pcpu-alloc: [0] 0 Built 1 zonelists, mobility grouping on. Total pages: 32512 Kernel command line: console=ttyUL0,9600 PID hash table entries: 512 (order: -1, 2048 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 121948K/131072K available (3765K kernel code, 121K rwdata, 1312K rodata) Kernel virtual memory layout: * 0xffffe000..0xfffff000 : fixmap * 0xffffe000..0xffffe000 : early ioremap * 0xf0000000..0xffffe000 : vmalloc & ioremap NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 irq-xilinx: /amba_pl/interrupt-controller@41200000: num_irq=5, edge=0x6 /amba_pl/timer@41c00000: irq=1 clocksource: xilinx_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_is xilinx_timer_shutdown xilinx_timer_set_periodic sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns Calibrating delay loop... 49.15 BogoMIPS (lpj=245760) pid_max: default: 4096 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) random: get_random_u32 called from bucket_table_alloc+0x2e4/0x35c with crng_ini0 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191s NET: Registered protocol family 16 clocksource: Switched to clocksource xilinx_clocksource NET: Registered protocol family 2 TCP established hash table entries: 1024 (order: 0, 4096 bytes) TCP bind hash table entries: 1024 (order: 2, 20480 bytes) TCP: Hash tables configured (established 1024 bind 1024) UDP hash table entries: 128 (order: 0, 6144 bytes) UDP-Lite hash table entries: 128 (order: 0, 6144 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. random: fast init done Skipping unavailable RESET gpio -2 (reset) workingset: timestamp_bits=30 max_order=15 bucket_order=0 io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) io scheduler mq-deadline registered io scheduler kyber registered Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 5, base_baud = 0) is a uartlie console [ttyUL0] enabled brd: module loaded libphy: Fixed MDIO Bus: probed xilinx_emaclite 40e00000.ethernet: Device Tree Probing xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus. xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF02 i2c /dev entries driver NET: Registered protocol family 17 Freeing unused kernel memory: 2296K This architecture does not have kernel memory protection. Hostname : nexys4ddr Kernel release : Linux 4.14.0-00493-gb68293ad2c93-dirty Kernel version : #120 Thu Dec 6 16:51:57 CET 2018 Please press Enter to activate this console. nexys4ddr:/# For the first I2C sensor (onboard ADT7420 sensor of the Nexys4 DDR board), we must use the /dev/i2c/0 (or /dev/i2c/i2c-0) character driver file (Major=89 minor=0). For the second I2C sensor (external TCN75A PMOD TMP3 sensor), we must use the /dev/i2c/1 (or /dev/i2c/i2c-1) character driver file (Major=89 minor=1). nexys4ddr:/# i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- 4b -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- nexys4ddr:/# i2cdetect -y 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- You can now use the Linux API for reading the I2C sensors... Pat.
  21. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar
  22. Hi, I'm working on ZYBO SoC. I want to boot it from QSPI flash but it fails anyhow. I have tried two methods using Vivado and IMPACT tool. 1. After successful implementation I created .bit and .bin files for a simple led_blinky project. Than I added "Configuration Memory Device" and selected Spansion s25fl128s 3.3v flash. I loaded the .bin file and then Erased, Verify and Programmed the flash step by step by checking the checkbox. The problem is with verify step. It fails every time. even then if I program it ignoring the failed verify step, it obliviously doesn't boots the program and no led blinks on board after resetting it. PS: I've taken care of the Jumpers already. 2. In the iMPACT tool I first created the PROM for a single FPGA, added 128MiB and created a .mcs file from the .bit file. then I initialized chain and after successful detection of board I added SPI Flash (which is attached above the ARM in the workspace figure) and loaded the flash with .mcs file. than I get option to either Erase, Verify or Program the flash. here too the program fails at Verify Step. Please help out.
  23. Hi, I am relatively new to working with the Zedboard. I've managed to get an I2C/I2S audio example working (using bare-metal) , that i've downloaded from here. http://www.zynqbook.com/download-tuts.html Now, I would like to get the same example working using the Linux Kernel. However, I can't seem to be able to access the I2C bus. The bus appears to be there, but denies access. zynq> i2cdetect -l i2c-0 i2c Cadence I2C at e0004000 I2C adapter zynq> i2cdetect -y 0 Error: Can't use SMBus Quick Write command on this bus From looking at the SDK, the I2C appears to be at 0xe0004000 Has any one got any suggestions, or point me in the right direction to find the correct settings..? Everywhere I have googled seem to provide i2c solutions for different boards, or bespoke platform setups. What I don't understand is why it just doesn't work "out-of-the-box" with the default settings. Or perhaps, i have missed something. I am using Xilinx SDK 2018.3, and the Xilinx kernel My kernel settings are these: CONFIG_REGMAP_I2C=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_CADENCE=y CONFIG_VIDEO_IR_I2C=y CONFIG_SND_SOC_I2C_AND_SPI=y CONFIG_RTC_I2C_AND_SPI=y My device tree looks like this: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; clocks = <0x1 0x26>; interrupt-parent = <0x4>; /*interrupts = <0x0 0x25 0x4>;*/ interrupts = <0x0 0x19 0x4>; reg = <0xe0004000 0x1000>; i2c-clk = <0x61a80>; #address-cells = <0x1>; #size-cells = <0x0>; }; The default device tree entry for i2c was disabled, so i've tried different combinations. Any help would be gratefully received Dave
  24. I want to use GNU RADIO to design an RF signal receiving circuit. For this I plan to use an FPGA card in the baseband section of the circuit (to handle the decimation and, if possible, to convert analogue to digital signal). My doubt lies in knowing if it is possible to communicate the FPGA card to the GNU RADIO application directly or if necessary from an external program. At this point it should be noted that I work in windows 10. I'm quite new on the subject of FPGA and GNU RADIO. I would really be grateful if you help me with this problem. The card is a Xilinx Zynq-7000 Developmet Board, the Z-7010, its features are best seen on the next page https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual Suggestions for design changes are welcome. In advance thanks for the help.