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  1. Pier

    zybo dma demo

    Hi , in none of the repos connected i can find the file zybo-z7-10-dma.xpr you mention in the instructions. eventually could you send a script for the block design ? Thanks
  2. Pier

    Zybo z7 evaluation

    How could be possible to implement the design shown in attached video? in the video the arrays are 600 samples each, but i would go for bigger arrays as possible and 24 or 32 bit values i'm planning to use a zybo z7 board exxample.mp4
  3. Hope you all are fine, I downloaded Digilent/Zybo-Z7-20-HDMI from https://github.com/Digilent/Zybo-Z7-20-HDMI I have upgraded the ip's, it was displaying output on monitor. Then I have created the ip of sobel edge detection and added the ip in block diagram. After solving some clocking issues, bitstream has been generated. After launching to sdk, when I Launch on Hardware (System Debugger), output doesn't display. Below is block diagram, please guide me
  4. Hi there, I have been not having luck in reading the aux pins on the zybo z7 board. I have setup the system as below: The XADC is setup with DRP and channel sequencer in continuous mode, with the setup as below: I can read the voltages on the XADC system monitor dashboard as below: But the XADC only read 0x5999 on Aux 15 Pin, as seen below: As you will see above, Aux 6 and Aux 14 is stuck at 0x5999 and Aux 7 and Aux 15 is fixed at 0x5111. I don't get any errors only a critical warning: [Timing 38-282] The design failed to meet the tim
  5. Hi, Before I embark on creating my own model I thought I would ask if there is a Step file available for the above mentioned Zybo Z7 board. I have an action to build an enclosure around it (unless someone can point me to one that is available for sale) and the CAD model would be a huge time savings. Many thanks
  6. We are using PL section of the Zynq7000 to transfer data to another module b y creating a SPI IP Inside the PL. We want to know that the PMOD pins availvalble on the Zybo-Z710 board are using open drain or push-pull configuration ? Do they have something like a internal pull-up resistor ? Please let me know.. Regards Amol
  7. Hello, I have been successful in running the lwIP echo server on the Zybo Z7 board. However, I want to develop a web server on Zynq. I have gone through the lwIP documentation. However, in the discussion of this topic, I was successful in reading the .bin file from the SD card. Now I want to set up a web server on Zynq so I can command the server to read the .bin file from SD card and store it in the DDR. How do I start working on the web server. I have been searching a lot for the tutorial or anything that could make me understand in a simpler way but I failed to find any.!
  8. Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK?
  9. Hello, I'm working on an audio project with a Zybo Z7-10 board (with Vivado 2016.4), and as a starting point I'm trying to set it up as an audio passthrough. I've been working off of the DMA audio demo, but I can't seem to get it to output a continuous stream. Is there a way to modify it so that the sound input can be immediately routed to the output without having to record it first?
  10. Hi, I am trying to learn about Zynq APSoC using Zybo 7z020. I have successfully completed all steps of this tutorial :https://reference.digilentinc.com/vivado/getting-started-with-ipi/2018.2 I have a problem that Tera Term is always printing square brackets instead of the expected output as shown in this tutorial. I am using Vivado 2018.3 with SDK 2018.3 on Window 10. Below is the screen snapshot of the problem. Could anybody please help. Thank you very much Lrni
  11. Hello again, As I continue to experiment with this development kit, I would find it valuable to be able to capture Raw images. Is that possible to do somehow? I didn't see any mention of it in the Demo documentation but it is possible that I missed it. Thanks again -Ted
  12. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  13. Hi! A couple of months ago, I bought a ZYBO Z7-10 board for one of my university labs. Just recently, I was using the JE PMOD ports to interface with an external LCD display. The board was programmed through QSPI Flash through the micro USB port. Unfortunately, a external 5 volt supply leaked into the 3v3 JE PMOD peripheral when the board was powered through the micro USB port. I immediately turned off the power supply and the ZYBO board once this had happened. After turning back on the ZYBO with all PMOD connections detached (to test if the board was still functional), the defa
  14. Hi Dear Sirs, I will start to work with Zybo Z7 Development Board. But, I couldn't find any explanations about ESD & Safety protections and warnings for the board in the reference manual. Could you please provide it to me if there is anything special to protect the board from ESD? Because I don't wanna break the board when touching it. Thank you..
  15. Serial digital interface (SDI) is a digital video interface used with the most of professional video cameras. It uses BNC connector and operates at speeds of 3 Gb/s or about, depending on the standard. The more detailed specification can be found in wikipedia. Most of the SDI adapters for FPGA use FMC connectors, like this one. There is no FMC connector on Zybo Z7 board, but it does have multiple PMOD ports. Could they probably substitute? If some simple extra circuitry is required, we maybe could build it on the top of some generic PMOD adapter like this. My major doubts are, would such
  16. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.
  17. Hi, I have been following tutorials from Zynq book for Zybo Z7 board. In tutorial 5, where the zybo_audio_ctrl IP core is used, I can not get any audio data through my board. The tutorials are made for Zybo board, and I followed migration guide (to Zybo Z7), but still no success. Any help would be appreciated. Thanks
  18. I wanted to try the example Audio-DMA project but it went really bad. This is what I did and the output from Vivado and SDK 2017.4. Source the make_project.tcl. Update the ip because I must. Get eight critical warnings, e.g., [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . Generate output products. Generate HDL wrapper so I can extract the hardware. IIC ports names differ in the .xdc so I have to change them to capital letter (IIC). Also notice that the ja ports are there, I don't know why though. Generate the bitfile. Got 1715 warnings, mos
  19. I'm designing an application using the Audio CODEC of the Zybo Z7. I'm configuring the CODEC by I2C properly and could see data coming from the I2S. Then I realized that each time I programmed the FPGA, the Led 5 of the board was turning ON... even this LED is not at all part of my design!! Never mentioned in my constraints and never mentioned in the verilog wrapper. Then proceeding by elimination when analyzing the constraints, I realized that this LED was turned ON as soon as the I2S clock went enabled... with below constraints: NO LED TURNED ON ##I2S Audio Codec ##set
  20. I have a question about how to connect zybo z7 to a ADC with LVDS input and output running at 200MHz. The zybo z7 need to provide clock to the ADC at 200 MHz and receive data at this speed. The ADC's interface is indeed LVDS yet this zybo z7 board's IO bank are all 3.3V powered, which means that it cannot use the internal termination. I think I have two way to make it work. 1. transmit data and clock in a single-ended way and do the single-ended to differential conversion on my ADC board. 2. transmit data in LVCMOS33 and do level conversion in ADC board. The problems I have are
  21. Hi Guys, My application on linux requires two ethernet ports on the Zybo Z7 board. So I have recently bought a Pmod NIC100 card. I read the references and I have enabled the encx24j600 driver in the xilinx linux kernel. I have enabled SPI0 controller in vivado for the Z7 board. Correct me if I am wrong, but I reckon to use the enabled encx24j600 driver, I have to add the interrupts and registers under spi parent in the device tree but I don't know the specifics of what I have to add. Can someone please help me out? My intention is to get this board to appear as eth1 in xilinx li
  22. dgottesm

    Memory tutorial

    Hi I am beginning my foray into FPGA design, and I decided that the best to to learn would be to learn on the go, and learn as I go. I am using a Zybo Z7 7020, Windows 10, and Vivado 16.4 I have a project for school which will be using PMODs as IOs and the information will have to be saved to memory of the board I am wondering if there is a good tutorial which will help me learn how to access, read and write to the DDR3
  23. Hello guys, I'm starting to work with Zybo Z7-20, and I've read this in the Zybo Z7 Reference Manual: "It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design." Can anyone tell me how can I do this please? I just want to treat the Zynq as a standalone FPGA. Any examples on how to do that? Thank you!!!
  24. I've been trying to get the Zybo Z7-10 HDMI demo (link) to run on my board, but I can't seem to be able to compile the actual project (using Vivado 2017.3 on Windows 10). I created the project from the create_project.tcl script in the proj folder, and was able to generate the block diagram and wrapper. I upgraded the IP cores and verified that the xdc file was consistent with the wrapper. But when I try to generate a bistream, Vivado always seems to get stuck on route_design. I've left Vivado running for 4 hours and it still can't move past route_design, despite it still using ~30% of my CPU.