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Found 4 results

  1. I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I couldn't make it to properly work. Recently I've discovered, in this vivado repository constraint file, from line 66 to 72, that some timing constraints were missing, so I've added them into my design. Unfortunately, one of them is giving me a synthesis error. I'm posting the specific timing constraint that's giving me problems, and so the resulting error: create_generated_clock -name o_adc_clock_in
  2. Hello, We have been developing a real time data transfer application using Genesys ZU-3EG boards along with Zmod DAC/ADC pair. We previously built the application on Eclypse boards and now are migrating the design to Genesys boards. In the process, we have discovered that one of the two Genesys boards is failing to power up the DAC and ADC pods regardless of the fact that our designs are running exactly the same initialization protocols for both of them. We have verified this by inserting both the DAC and ADC pods to both Genesys boards and running some tests. On one board (board A),
  3. Hello, I am currently developing a project with the ZmodADC1410_Demo_Baremetal of Eclypse-z7. The development environment is vivado 2019.1. I use the lwip software protocol stack in the SDK, RAW API mode, and I want to use UDP through the Ethernet port on the PS side. Send the adc data to the PC (only the data of channel 1), I have now completed the spectrum analysis of the collected data on the PL side based on the adc demo, and then sent the data to the sCH1in [13:0 ] Port of the ZmodADC1410AxiAdapter IP, now I have encountered difficulties in writing the PS-side program. I am conf
  4. I am in the proposal process that utilizes the Eclypse Z7 along with the Zmod ADC 1410. We are hoping to utilize vetted code to configure the ADC and accept the sample data. We need to do some processing and interfacing to external components so we cannot use the provided bit file. I have looked over GitHub repository ( and couldn’t find any VHDL or Verilog files?