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Found 105 results

  1. tiago0297

    Axi DMA always busy

    Hi, I'm doing a project that uses AXI DMA. I already done my Ip Core, my Block Design e and my SDK code. The problem is that when my program reaches while(XAxiDma_Busy(&axiDma, XAXIDMA_DMA_TO_DEVICE)) it gets stuck. I'm using a Zedboard and Vivado 2017.4. I did a search, found out that it's a very popular problem, but I had no success solving it, so I'm posting here trying to get more help. I'm attaching my sources. Thank you
  2. AJS


    Hello, I am trying to display text on an image using the libraries provided . I am able to load the image and print text separately but when an image is loaded and i try to display text on it, it does not seem to print. How can i print text on a image loaded from sd card present in Pmod MTDS. With Regards, Ajs
  3. JeffL

    Zedboard 3.3V Aux

    I'm planning to attach a mezzanine card to the Zedboard via the board's ASP-134603-01 FMC connector. I'm noting all of the 3.3V pins (VCC3V3) to provide power to the mezzanine card, and I noticed pin D32 of the FMC connector signal name is 3V3AUX. I looked all over the datasheet and schematic, but I don't know what 3V3AUX is supposed to do. Is pin D32 an additional pin that can provide 3.3V of power or is it an input pin that accepts 3.3V and it powers other circuitry on the development board? Any help would be greatly appreciated. Thanks.
  4. Akshay Bhat

    Pmod MTDS display on ZED board

    Hello , I am using the Pmod AD5 and Pmod MTDS on the Zedboard I am connecting the pmod AD5 with a simple POT and giving different values it. From the demo example in the mtds ip I got to know that display images are store in the file with .bmp in SD card then invoked when needed My problem is i have nearly 500 values in to be displayed so , my question Is there any way to dynamically generate the .bmp file to the MTDS and display it when we give the different values from the AD5 ? Regards Akshay
  5. Hi, I am trying to create and install an application for Zynq using PetaLinux. I have created a new project as per ug980 and have created an app as per ug981. When I run 'petalinux-build -c rootfs/myapp' it fails with ERROR: Nothing PROVIDES 'rootfs/myapp'. I have not edited the source code. I am just trying to build myapp into the existing system image. Another observation is, when I built gpio-demo. It threw ERROR: Nothing PROVIDES 'rootfs/gpio-demo'. Close matches: gpio-demo. I am wondering what would have caused the error.
  6. Bharath

    Zedboard Zynq 7000 XADC Header

    Hi, I'm trying to measure an external Voltage connected to the AUX0 pin of the XADC header using Zedboard .While measuring the output I find that the voltage is shows higher value by factor 3 or even 4 of the input differential voltage applied. I'm unable to figure out why this is happening. C code file is attached also. I have followed the following thread while performing my project too I have connected AUXP0 to 0.2 V and AUXN0 to GND . Could someone help on this?? helloworld.c
  7. Sridhar Prasath Aruppukottai Ganesan

    gsm module connection with zedboard

    Greetings, My project is to send some data to http server from zedboard via GSM module(through AT commands). I have designed the hardware connection in vivado (conected rx,tx,vcc and gnd pins in JB connector) . I have set the baudrate to 115200(for module hilo) and I think I am sure that the tx and rx pins are perfectly working. Now my question is how to send AT commands to GSM module. For those who dont know about GSM module , I ll just brief about its working. Basically in GSM modules, if some characters(AT COMMANDS) are typed and sent , the GSM module will respond with some characters. For example, 1. If I type 'A','T' (2 characters in this case) , the response from GSM module will be OK('O','K') 2. If I type 'A','T','+','C','P','I','N','?' (7 characters), the response will be 'C','P','I','N',':','R','E','A','D','Y' (CPIN:READY) So basically I have to send some commands from tx pin of zedboard to rx pin of GSM module. And I have to receive some response from tx pin of GSM to rx pin of zedboard. Hope everybody gets the basic idea.(only for those who doesnt know abt GSM module. Not for pros😀) So I have wrote some code, which will send the commands to the baseaddress of UARTLITE ( I have used AXI UARTLITE for this module). The problem is that I m sending the data to the UARTLITE address and searching for the response from the same UARTLITE baseaddres. But I dont know from which address to read the response back.. Hope all got my question. For your convenience, I will post some part of the code. unsigned char Sender1[] = {'A','T','\0'}; unsigned char Sender2[] = {'A','T','D','+','4','9','1','7','6','3','0','1','7','4','8','1','4',';','\0'}; int Index =0; int i = 0; int u=0; SendBuffer[Index]='\0'; RecvBuffer[Index]='\0'; while(Sender != '\0'){ for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) { SendBuffer[Index] = Sender[i+Index]; XUartLite_SendByte(UARTLITE_BASEADDR, SendBuffer[Index]); } for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) { RecvBuffer[Index] = XUartLite_RecvByte(UARTLITE_BASEADDR); Receiver[i+Index] = RecvBuffer[Index]; } i = i + TEST_BUFFER_SIZE; u++;
  8. Sridhar Prasath Aruppukottai Ganesan

    PmodGps connection to Zedboard

    Hello all, I have connected PmodGps to JA connector of zedboard. I have downloaded the pmod example code(Microblaze) and did a little modification for Zynq devices. The code is listed below. For some reasons the code does not seem to be working. (The build is finished but there is blank terminal. Its not going inside that while loop. Probably because GPS.Ping does not get any data). And there is a minor warning in one of the files of BSP (bsp -> ps7_coretexa9_0 -> libsrc -> PmodGps_v1_1 - > src - PmodGPSselftest.c). I have attached the screenshots for better understanding. Please help me with this. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- /************ Include Files ************/ #include "PmodGPS.h" #include "xil_cache.h" #include "xparameters.h" #include "xil_printf.h" /************ Macro Definitions ************/ #ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ #define PERIPHERAL_CLK 100000000 // FCLK0 frequency is not in xparameters.h for some reason #else #define PERIPHERAL_CLK XPAR_CPU_M_AXI_DP_FREQ_HZ #endif /************ Function Prototypes ************/ void DemoInitialize(); void DemoRun(); /************ Global Variables ************/ PmodGPS GPS; /************ Function Definitions ************/ int main(void) { DemoInitialize(); DemoRun(); return 0; } void DemoInitialize() { GPS_begin(&GPS, XPAR_PMODGPS_0_AXI_LITE_GPIO_BASEADDR , XPAR_PMODGPS_0_AXI_LITE_UART_BASEADDR, XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ); GPS_setUpdateRate(&GPS, 1000); } void DemoRun() { while (1) { if ( { GPS_formatSentence(&GPS); if (GPS_isFixed(&GPS)) { xil_printf("Latitude: %s\n\r", GPS_getLatitude(&GPS)); xil_printf("Longitude: %s\n\r", GPS_getLongitude(&GPS)); xil_printf("Altitude: %s\n\r", GPS_getAltitudeString(&GPS)); xil_printf("Number of Satellites: %d\n\n\r", GPS_getNumSats(&GPS)); } else { xil_printf("Number of Satellites: %d\n\r", GPS_getNumSats(&GPS)); } = FALSE; } } } -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  9. Hello, I am using Zed board 7000. I want to do Image Processing or basic computation in Zed board on PL side using FPGA. I was a bit confused to start either with a Linux image(PetaLinux or Xillinux) or directly through the Vivado software. Is it possible to do any computation or Image Processing on the PL side using ARM processor only to interface the peripherals(I don't want the computation to be done on the ARM processor). Kindly provide any reference link or tutorial which can address my queries. Thanks in advance. ---Nikith--
  10. Hello I bought a zed board days ago,to learn fpga . I received a DVD of an old VIVADO DESIGN SUITE 2014 And a voucher OEM ZYNQ 7000 SOC XC7Z020 VIVADO DESIGN EDITION VOUCHER Now in 2018,not understand what best edition to install,that in CD, get the best,I m interested in particular to HLS. From forums seems that the free webpack has already all. The voucher what gives me more? Thank you
  11. Sridhar Prasath Aruppukottai Ganesan

    Zedboard- connected GPS device on UART0- Viewing streaming gps data on PC terminal

    Greetings all, This might be a basic question. I have connected a GPS module (gtpa010) tx and rx pins to UART0 port(EMIO pins JA2 and JA4 of JA connectors). Its baud rate is 9600. So i have changed the baudrate to 9600 in the configuration of UART0. So i have created the hardware design, added the constraints for the EMIO pins. set_property PACKAGE_PIN AA11 [get_ports UART_0_rxd] set_property PACKAGE_PIN AA9 [get_ports UART_0_txd] set_property IOSTANDARD LVCMOS25 [get_ports UART_0_*] set_property PULLDOWN true [get_ports UART_0_*] So I have exported the hardware and launched the SDK and created basic program for viewing the serial data coming on UART0. I have attached the program as well. I donno whether it is correct or not. What should i do to view the serial data on PC terminal that has been coming through UART 0.?? int main() { XUartPs_Config *Uartpsconfig; XUartPs myuartps; int Status; init_platform(); Uartpsconfig= XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID); XUartPs_CfgInitialize(&myuartps, Uartpsconfig, Uartpsconfig->BaseAddress); while(1){ Status= XUartPs_SelfTest(&myuartps); printf("gps data : %d", Status); cleanup_platform(); return 0; } } This might me wrong .So help me with this
  12. Greetings all, I am new to zedboard. This might be a basic question. I want to send some data via UART0 to DDR memory through direct memory access AXI. (GPS data) Again I want to collect another set of data from UART1 and writing it to DDR memory.(GSM/LTE module) Now if interrupt from one UART( UART1) occurs, I want the processed data of UART0 which is on the DDR memory to be read via UART1(GSM module) and send to a remote server. Any suggestions and advice on how can i design the hardware?
  13. Hi, I'm running Arch Linux ( on Zedboard and I'd like to use the OTG-USB as a host, but my Zedboard doesn't seem to detect the device plugged in (I've tried a USB flash drive). What are your suggestions? I've followed the instructions on , but Zedboard just won't see the device.
  14. sourav


    How to use the FMC LPC pins in the zedboard.. How many digital inputs i can give through it? any proper reference manual may help..
  15. JakeWhitt

    Connecting a GigE Camera to my Zedboard

    Basically I was wondering if it were possible to connect an Allied Vision GigE camera to my zedboard? I am using the Mako G030B model, and was hoping to be able to process the data to run it through some algorithms. I was intending on just using the ethernet cable from the camera to the FPGA, however if there is a better input please let me know! If there are any additional questions needed please ask!
  16. Dear Experts I am currently using Petalinux 2015.4 on Zedboard. I have connected a Transcend CF Card through USB 2250 Evaluation Board through USB-OTG. Now the issue I am facing right now is I can't hot swap CF cards, i.e. if I plug out the CF card from EVB and plug it in, the linux doesnot enumerates it until Zedboard is restarted. Kindly help me in this issue. P.S. I got USB-OTG working by adding following lines to system-top.dts: /dts-v1/; /include/ "system-conf.dtsi" /{ usb_phy0:phy0 { compatible="ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port=<0x170>; drv-vbus; }; }; &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; } ; Regards
  17. Hello, I am using the ZedBoard and FMCOMMS3 to receive data in two channels (I am programming with Matlab toolbox). I am using an IF of 25KHz and Fs of 2 MHz. Since I get a warining : "1 samples from the radio have been lost", I am trying to use the burst mode. When I do that, I do not lose samples any more, since they are stored in the buffer and then processed. The problem is that I want to measure in real-time. I am processing the next example:1. I send a -50 dBm signal with a signal generator to the zedboard and I capture the data.2. I change the output power of the signal generator to -40 dBm. I capture the data, and I expect to get this -40 dBm, but I still get -50 dBm because the buffer was filled with the previous signal.Is there a way to flush the buffer of the sdrrx object before capturing the new set of data (-40 dBm) in the burst mode?The other option if to use the normal mode, without burst mode enabled, but in that way I lose samples and I guess that in that way I can not completely trust the phase stimation I get from the signal. Thanks very much.
  18. Hello! In the hardware user's guide of the ZedBoard I read the following: "Four Pmod connectors interface to the PL-side of the EPP. These will connect to EPP Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side of the EPP on MIO pins [7,9-15] in EPP MIO Bank 0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog). Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs." My question is: Can I use ALL of those Pmod ports to connect the external ADC add-on boards "Pmod AD1" and "Pmod AD2" to them? Or can those ADC add-on boards only be used with a certain type of Pmod port, for example only with a Pmod connector that is connected to the PL, only with a Pmod connector that does not have differentially routed conductors for LVDS, etc.? Best regards!
  19. Hello, I tried to Embedded Linux kernel build with Zedboard, and I refer to However, When I try this page, I faced something strange. Because, This git hasn't include "digilent_zed_defconfig" What was wrong? I'm working with Ubuntu 16.04 LTS / Xilinx ISE 14.7 Webpack
  20. lucabe

    Zedboard FMC-LPC connection

    Hi, I'm an unexperienced Zedboard user. I want to connect to the FMC-LPC connector, and route those signals to another board. How can I do it? Possibly using components that I can solder by hand. I asked the question at the Zedboard support forum and they replied "Please ask your question over at digilent as they are the main contact for educational support." Thank you.
  21. deppenkaiser


    Hello, i have an other question: If i look in the Mouser electronic shop i see, that the zedboard is associated with digilent and you Show on the board. Why do you have no support on for the zedboard? Thank you...
  22. Hi everybody, thaks for your time. I'm a new Xilinx user and I'm learning about VHDL language and FPGA. In this opportunity, I want to establish a I2C communication between Zedboard and PmodACL. I'm implementing the tutorial "Getting Started with Digilent Pmod IPs", and I have some doubts: 1) I've installed the "vivado-library-2015.4-3", but when I search the info in board section about Pmod there is nothing: 2) When I click on "Generate Bitstream" I get this error: With this lines: Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 8 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin1_iobuf/IBUF (in pmod_out_pin1_iobuf macro) has no loads. An input buffer must drive an internal load. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin4_iobuf/IBUF (in pmod_out_pin4_iobuf macro) has no loads. An input buffer must drive an internal load. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. I think it's because in the block design I could not open the Pmod corresponding to the Zedboard and then the pin assignment is not elaborated. So, how can i do to import the complete library for Zedboard pmod? Or, which is the order for Pmod pin assignment? Bests reggards, Oscar.
  23. rockxito32

    Usign multiple PmodACL with Zedboard by SPI

    Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  24. Hi, I am relatively new to FPGA programming and purchased recently the Zedboard. I am trying to implement a simple blinky Verilog design, written in Vivado, on the Zedboard. The Zedboard is connected via two ordinary USB cables to the Laptop - one from J17, one from J14. I am able to log into the Linux part of the Zynq and do all demos, but have no success implementing the blinky design into the FPGA part due to the "Program Device" option in Vivado staying grayed out after generating successfully the bitstream and trying to connect to the device. There seems to be an issue with the connection to the board (I am getting the message board not connected or not powered). The last step to "Program Device" is never available. I tried about 10 installations with different Vivado WebPack revisions and on 3 different laptops (2 with Windows 10, one with Windows 7). I tried also updating cable drivers and modifying the jumpers JP7 to 11 to different configurations. "Program Device" stays grayed out. I am out of ideas and am hoping someone can give me a hint what is going wrong. Thanks
  25. ArcaGraphy

    Pront character on OLED - ZedBoard

    Hi, In my project I want to print alphanumeric data on the OLED display on the ZedBoard, but do that by usin GPIO. I have found a couple of related IP cores online, but that is not what I need. I need something simililar like logo.bin file that is the defoult Digilent logo that apears on the OLED when the Linux is booted. So any possibilitis to modify the logo.bin, or to create .bin file with my own contents? I appriciate your tips and help!