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Found 94 results

  1. Greetings all, I am new to zedboard. This might be a basic question. I want to send some data via UART0 to DDR memory through direct memory access AXI. (GPS data) Again I want to collect another set of data from UART1 and writing it to DDR memory.(GSM/LTE module) Now if interrupt from one UART( UART1) occurs, I want the processed data of UART0 which is on the DDR memory to be read via UART1(GSM module) and send to a remote server. Any suggestions and advice on how can i design the hardware?
  2. Hi, I'm running Arch Linux (https://archlinuxarm.org/platforms/armv7/xilinx/zedboard) on Zedboard and I'd like to use the OTG-USB as a host, but my Zedboard doesn't seem to detect the device plugged in (I've tried a USB flash drive). What are your suggestions? I've followed the instructions on http://zedboard.org/sites/default/files/documentations/GS-AES-Z7EV-7Z020-G-V7-1.pdf , but Zedboard just won't see the device.
  3. sourav

    FMC LPC

    How to use the FMC LPC pins in the zedboard.. How many digital inputs i can give through it? any proper reference manual may help..
  4. JakeWhitt

    Connecting a GigE Camera to my Zedboard

    Basically I was wondering if it were possible to connect an Allied Vision GigE camera to my zedboard? I am using the Mako G030B model, and was hoping to be able to process the data to run it through some algorithms. I was intending on just using the ethernet cable from the camera to the FPGA, however if there is a better input please let me know! If there are any additional questions needed please ask!
  5. Dear Experts I am currently using Petalinux 2015.4 on Zedboard. I have connected a Transcend CF Card through USB 2250 Evaluation Board through USB-OTG. Now the issue I am facing right now is I can't hot swap CF cards, i.e. if I plug out the CF card from EVB and plug it in, the linux doesnot enumerates it until Zedboard is restarted. Kindly help me in this issue. P.S. I got USB-OTG working by adding following lines to system-top.dts: /dts-v1/; /include/ "system-conf.dtsi" /{ usb_phy0:phy0 { compatible="ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port=<0x170>; drv-vbus; }; }; &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; } ; Regards
  6. Hello, I am using the ZedBoard and FMCOMMS3 to receive data in two channels (I am programming with Matlab toolbox). I am using an IF of 25KHz and Fs of 2 MHz. Since I get a warining : "1 samples from the radio have been lost", I am trying to use the burst mode. When I do that, I do not lose samples any more, since they are stored in the buffer and then processed. The problem is that I want to measure in real-time. I am processing the next example:1. I send a -50 dBm signal with a signal generator to the zedboard and I capture the data.2. I change the output power of the signal generator to -40 dBm. I capture the data, and I expect to get this -40 dBm, but I still get -50 dBm because the buffer was filled with the previous signal.Is there a way to flush the buffer of the sdrrx object before capturing the new set of data (-40 dBm) in the burst mode?The other option if to use the normal mode, without burst mode enabled, but in that way I lose samples and I guess that in that way I can not completely trust the phase stimation I get from the signal. Thanks very much.
  7. Hello! In the hardware user's guide of the ZedBoard I read the following: "Four Pmod connectors interface to the PL-side of the EPP. These will connect to EPP Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side of the EPP on MIO pins [7,9-15] in EPP MIO Bank 0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog). Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs." My question is: Can I use ALL of those Pmod ports to connect the external ADC add-on boards "Pmod AD1" and "Pmod AD2" to them? Or can those ADC add-on boards only be used with a certain type of Pmod port, for example only with a Pmod connector that is connected to the PL, only with a Pmod connector that does not have differentially routed conductors for LVDS, etc.? Best regards!
  8. Hello, I tried to Embedded Linux kernel build with Zedboard, and I refer to http://www.wmelectronic.at/PDFS/digilent/ZedBoard_GSwEL_Guide.pdf However, When I try this page, I faced something strange. https://github.com/Digilent/linux-digilent Because, This git hasn't include "digilent_zed_defconfig" What was wrong? I'm working with Ubuntu 16.04 LTS / Xilinx ISE 14.7 Webpack
  9. lucabe

    Zedboard FMC-LPC connection

    Hi, I'm an unexperienced Zedboard user. I want to connect to the FMC-LPC connector, and route those signals to another board. How can I do it? Possibly using components that I can solder by hand. I asked the question at the Zedboard support forum and they replied "Please ask your question over at digilent as they are the main contact for educational support." Thank you.
  10. deppenkaiser

    Zedboard

    Hello, i have an other question: If i look in the Mouser electronic shop i see, that the zedboard is associated with digilent and you Show on https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ the board. Why do you have no support on https://reference.digilentinc.com/reference/software/petalinux/start for the zedboard? Thank you...
  11. Hi everybody, thaks for your time. I'm a new Xilinx user and I'm learning about VHDL language and FPGA. In this opportunity, I want to establish a I2C communication between Zedboard and PmodACL. I'm implementing the tutorial "Getting Started with Digilent Pmod IPs", and I have some doubts: 1) I've installed the "vivado-library-2015.4-3", but when I search the info in board section about Pmod there is nothing: 2) When I click on "Generate Bitstream" I get this error: With this lines: Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 8 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin1_iobuf/IBUF (in pmod_out_pin1_iobuf macro) has no loads. An input buffer must drive an internal load. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin4_iobuf/IBUF (in pmod_out_pin4_iobuf macro) has no loads. An input buffer must drive an internal load. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. I think it's because in the block design I could not open the Pmod corresponding to the Zedboard and then the pin assignment is not elaborated. So, how can i do to import the complete library for Zedboard pmod? Or, which is the order for Pmod pin assignment? Bests reggards, Oscar.
  12. rockxito32

    Usign multiple PmodACL with Zedboard by SPI

    Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  13. Hi, I am relatively new to FPGA programming and purchased recently the Zedboard. I am trying to implement a simple blinky Verilog design, written in Vivado, on the Zedboard. The Zedboard is connected via two ordinary USB cables to the Laptop - one from J17, one from J14. I am able to log into the Linux part of the Zynq and do all demos, but have no success implementing the blinky design into the FPGA part due to the "Program Device" option in Vivado staying grayed out after generating successfully the bitstream and trying to connect to the device. There seems to be an issue with the connection to the board (I am getting the message board not connected or not powered). The last step to "Program Device" is never available. I tried about 10 installations with different Vivado WebPack revisions and on 3 different laptops (2 with Windows 10, one with Windows 7). I tried also updating cable drivers and modifying the jumpers JP7 to 11 to different configurations. "Program Device" stays grayed out. I am out of ideas and am hoping someone can give me a hint what is going wrong. Thanks
  14. ArcaGraphy

    Pront character on OLED - ZedBoard

    Hi, In my project I want to print alphanumeric data on the OLED display on the ZedBoard, but do that by usin GPIO. I have found a couple of related IP cores online, but that is not what I need. I need something simililar like logo.bin file that is the defoult Digilent logo that apears on the OLED when the Linux is booted. So any possibilitis to modify the logo.bin, or to create .bin file with my own contents? I appriciate your tips and help!
  15. cvtabc

    Best Vivado license option on Zedboards

    Hello I want to buy a Zedboard to evaluate to possibly replacing our existing embedded computer solution (Kontron ETX computer module on a baseboard) with a ZYNQ 7000 based solution. I work at a research institute with a very strong mandate to train students. We will probably put a student on this job to investigate, so we might be able to qualify for the Academic edition of the Zedboard. My question is related to the licenses (vouchers) that come bundled with the zedboards by the various resellers. 1. On the zedboard.org site http://zedboard.org/sites/default/files/product_briefs/PB-AES-Z7EV-7Z020_G-v12.pdf they state: A. (AES-Z7EV-7Z020-G) ZedBoard Commercial Edition (Available Exclusively from Avnet) I have contacted local Avnet rep which stated that this board comes with the Vivado HL Design edition node lock licence valid for 1 year. B. (ZEDBOARD) ZedBoard Academic Edition (Available Exclusively from Digilent) I have contacted digilent which indicate that this board comes with a node locked SDSoC licence valid for 1 year. 2. Looking at other suppliers like Digikey and Mouser (http://www.digikey.com/products/en?keywords=ZEDBOARD) you find -when searching the datasheet- that they provide a voucher for Chipscope licence only. You use webpack with these boards. Now I know that Vivado Webpack should be enough but I want to maximize value by purchasing the most valuable license for our particular application. I would want the student to have maximum flexibility. I think elements that are important are. 1. Good simulation and debugging capabilities i.e. embedded logic analyser, chipscope and a version of ISIM with more features than that shipped with webpack. 2. Good tools for C/C++ software development. We would be looking at integrating EPICS in our solutions. 3. Also access to more IP cores not available in Webpack would also be interesting to evaluate. We would be looking at integrating EtherCAT into our solutions. 4. It would also be nice to do High Level synthesis work (HLS) using C. Please advise me on which resellers' product supply the best/most valuable licensing option. Thank you Chris
  16. mihai5

    Connect Zedboard through VirtualBox

    Hi, I want to connect my zedboard to virtual machine (Ubuntu 16.04 64 bit in VirtualBox). When i try to connect throught XMD console to zedboard, it appears that the cable is not connected. Can anyone help me with some hints or advices ?
  17. Dear Experts, I have a Zedboard and I am running Petallinux 2015.4, now I want to read and write to file that should be stored on QSPI. I followed this tutorial, http://www.wiki.xilinx.com/Zynq+QSPI+Driver but when I write cat /proc/mtd, it does not show any partitions but my device tree contains the same partitions. Kindly help me in this regard. Regards
  18. Hi, we are using AVNET ZedBoard and we would like to pull out a control signal from our Pmod port. Now the voltage can only reach 2.5V from Jc and Jd port, and reach 0.75V from Ja and Jb port. However, we need a voltage greater than 3V to drive our add-on mux. Is that possible for a PMOD to reach 3V on the ZedBoard? Thank you very much. Angie
  19. Dear Experts I need help regarding interrupt handling using UIO. I am using Vivado 2015.4 and Petalinux 2015.4. The board used is Zedboard. I made the following vivado project attached as image. The interrupts from AXI and Fabric (PL-PS) are enabled. Afterwards i was able to export it as UIO and it shows in /dev as uio0. Now I implemented the following code by following this link: My code is as follows: /* * File: main.c * Author: fss * * Created on August 23, 2017, 12:35 PM */ #include <sys/mman.h> #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include <poll.h> #include <fcntl.h> #include <errno.h> #define GPIO_DATA_OFFSET 0x00 #define GPIO_TRI_OFFSET 0x04 #define GPIO_DATA2_OFFSET 0x08 #define GPIO_TRI2_OFFSET 0x0C #define GPIO_GLOBAL_IRQ 0x11C #define GPIO_IRQ_CONTROL 0x128 #define GPIO_IRQ_STATUS 0x120 unsigned int get_memory_size(char *sysfs_path_file) { FILE *size_fp; unsigned int size; // open the file that describes the memory range size that is based on the // reg property of the node in the device tree size_fp = fopen(sysfs_path_file, "r"); if (size_fp == NULL) { printf("unable to open the uio size file\n"); exit(-1); } // get the size which is an ASCII string such as 0xXXXXXXXX and then be stop // using the file fscanf(size_fp, "0x%08X", &size); fclose(size_fp); return size; } void reg_write(void *reg_base, unsigned long offset, unsigned long value) { *((volatile unsigned long *)(reg_base + offset)) = value; } unsigned long reg_read(void *reg_base, unsigned long offset) { return *((volatile unsigned long *)(reg_base + offset)); } uint8_t wait_for_interrupt(int fd_int, void *gpio_ptr) { static unsigned int count = 0, bntd_flag = 0, bntu_flag = 0; int flag_end=0; int pending = 0; int reenable = 1; unsigned int reg; unsigned int value; // block (timeout for poll) on the file waiting for an interrupt struct pollfd fds = { .fd = fd_int, .events = POLLIN, }; int ret = poll(&fds, 1, 100); printf("ret is : %d\n", ret); if (ret >= 1) { read(fd_int, (void *)&reenable, sizeof(int)); // &reenable -> &pending // channel 1 reading value = reg_read(gpio_ptr, GPIO_DATA_OFFSET); if ((value & 0x00000001) != 0) { printf("Interrupt recieved"); } count++; usleep(50000); // anti rebond if(count == 10) flag_end = 1; // the interrupt occurred for the 1st GPIO channel so clear it reg = reg_read(gpio_ptr, GPIO_IRQ_STATUS); if (reg != 0) reg_write(gpio_ptr, GPIO_IRQ_STATUS, 1); // re-enable the interrupt in the interrupt controller thru the // the UIO subsystem now that it's been handled write(fd_int, (void *)&reenable, sizeof(int)); } return ret; } int main(void) { int fd = open("/dev/uio0", O_RDWR); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } int gpio_size = get_memory_size("/sys/class/uio/uio0/maps/map0/size"); /* mmap the UIO devices */ void * ptr_axi_gpio = mmap(NULL, gpio_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); while (1) { wait_for_interrupt(fd,ptr_axi_gpio); } close(fd); exit(EXIT_SUCCESS); } But the issue is that this code is not catching the interrupt. Kindly help me in this. Any suggestion/links are more than welcomed Regards
  20. peelza

    AXI DMA

    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. https://github.com/mstuehn/dma_proxy Any help is appreciates Best regards,
  21. Colin

    Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from http://www.zynqbook.com/download-tuts.html and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me what am i doing wrong despite the fact im doing the tutorial step for step?
  22. peelza

    Petalinux Kernel module

    Hi I want to transfer data from PL to PS via DMA. I am using zedboard. I am using petalinux in the PS. i have created a module for the DMA called "axidma". i have a header file in the module named axidma.h where i have defined some macros. axidma.h and axidma.c are in the same directory. Now i want to use those macros in user space applicatiion but i cannot access them. I know it is possible by changing the makefile of the module but i am not an expert in makefiles so i dont know how to do that. Any help will be appreciated
  23. Hello, is the ADC of Zedboard able to sample negative signals? And what are the specifications of the ADC built in? Thank You! Best regards
  24. mosambers

    Using Pmod of PS-Side of Zedboard

    Hello, I am trying to generate a Digital Output by using the Zynq Processing System. I tought using the Pmod would be easy to handle but I am already failing to design the hardware to activate the Pmod MIO. Do you know a (or similar) tutorial for that? Can you give some advises how to realize it? Thank You! Best regards
  25. Hello, is it possible to sample an external analog signal using the XADC? Or do I need the AMS101 Eval-Card for that? I'm using the Sony XC-HR50 analog Camera (datasheet: https://pro.sony.com/bbsc/ssr/product-XCHR50/ ), which has a CCD Sensor. I am very new to Zedboard and trying do save the picture of the camera. Thank you, kind regards The Video Output is shown below: