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Found 76 results

  1. Hello, is it possible to sample an external analog signal using the XADC? Or do I need the AMS101 Eval-Card for that? I'm using the Sony XC-HR50 analog Camera (datasheet: https://pro.sony.com/bbsc/ssr/product-XCHR50/ ), which has a CCD Sensor. I am very new to Zedboard and trying do save the picture of the camera. Thank you, kind regards The Video Output is shown below:
  2. Dear MembersI am working on Petalinux 2015.4 and ZedBoard, I am trying to connect a CF Card through USB OTG, but the device doesnot gets registered and won't show up in /dev and I cannot mount it. Kindly help me in this regard.Regard
  3. Vmodcam problems

    Hi, I am using vmodcam and have problem with image resolution and bad pixels. I have microZed 7010 board and I/O carrier and try to send image via Ethernet. First problem is, I set all the register values mentioned in the rm (https://reference.digilentinc.com/_media/vmodcam/vmodcam_rm.pdf) to get image with resolution 1600x1200 px. Unfortunately I got image containing 4 frames with resolution 800x600 px (attachment: bad_res_image.jpg). Before logging image I saw values in these registers via I2C and everything in the register is set as in the rm. Do you have any idea what is wrong? Second problem is more serious. In this link I send the results when I show only 800x600 px of the image (https://imgur.com/a/nmviB). - in 70% of cases the image I get is wrong (picture 3, 4 in the link) - in 10% of cases the image I get is shifted in some places and but we can recognize the shape (picture 5 in the link) - in 20% of cases I get image which is OK (picture 1, 2 in the link) But in 100% of cases my image have bad pixels. I would really appreciate any help or even only a hint. Thank you in advance! Best regards czajak
  4. Dear Experts I am using Petalinux 2015.4 and Zedboard. I am reading a GPIO which is supposed to go from 0 to 1 and in commandline, I can see that it happens. But when I execute it in the code, the value always remain 0 as initial value is 0. My code is as follows: int number=-1; unsigned char error = 0; int fd_done; //Export GPIO fd_done = open("/sys/class/gpio/export", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Export Failed\n\r"); #endif error=1; } write(fd_done,"903",3); close(fd_done); //Set GPIO as input fd_done = open("/sys/class/gpio/gpio903/direction", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Direction Failed\n\r"); #endif error=1; } write(fd_done,"in",2); close(fd_done); char value; fd_done = open("/sys/class/gpio/gpio903/value", O_WRONLY); lseek(fd_done, 0, SEEK_SET); read(fd_done, &value, 8); printf("Done Value: \t %d \n",value); close(fd_done); fd_done = open("/sys/class/gpio/unexport", O_WRONLY); write( fd_done,"903",3); close(fd_done); return number;
  5. Dear Expert I am working on Petalinux 2015.4 and Zedboard. I want to have a contagious 4 MB block of DDR to communicate with PL and have the physical address of the its Base. -Can I have this much memory allocated? -How can I get physical address of the memory? Regards
  6. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  7. Dear Experts I need help regarding interrupt handling using UIO. I am using Vivado 2015.4 and Petalinux 2015.4. The board used is Zedboard. I made the following vivado project attached as image. The interrupts from AXI and Fabric (PL-PS) are enabled. Afterwards i was able to export it as UIO and it shows in /dev as uio0. Now I implemented the following code by following this link: My code is as follows: /* * File: main.c * Author: fss * * Created on August 23, 2017, 12:35 PM */ #include <sys/mman.h> #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include <poll.h> #include <fcntl.h> #include <errno.h> #define GPIO_DATA_OFFSET 0x00 #define GPIO_TRI_OFFSET 0x04 #define GPIO_DATA2_OFFSET 0x08 #define GPIO_TRI2_OFFSET 0x0C #define GPIO_GLOBAL_IRQ 0x11C #define GPIO_IRQ_CONTROL 0x128 #define GPIO_IRQ_STATUS 0x120 unsigned int get_memory_size(char *sysfs_path_file) { FILE *size_fp; unsigned int size; // open the file that describes the memory range size that is based on the // reg property of the node in the device tree size_fp = fopen(sysfs_path_file, "r"); if (size_fp == NULL) { printf("unable to open the uio size file\n"); exit(-1); } // get the size which is an ASCII string such as 0xXXXXXXXX and then be stop // using the file fscanf(size_fp, "0x%08X", &size); fclose(size_fp); return size; } void reg_write(void *reg_base, unsigned long offset, unsigned long value) { *((volatile unsigned long *)(reg_base + offset)) = value; } unsigned long reg_read(void *reg_base, unsigned long offset) { return *((volatile unsigned long *)(reg_base + offset)); } uint8_t wait_for_interrupt(int fd_int, void *gpio_ptr) { static unsigned int count = 0, bntd_flag = 0, bntu_flag = 0; int flag_end=0; int pending = 0; int reenable = 1; unsigned int reg; unsigned int value; // block (timeout for poll) on the file waiting for an interrupt struct pollfd fds = { .fd = fd_int, .events = POLLIN, }; int ret = poll(&fds, 1, 100); printf("ret is : %d\n", ret); if (ret >= 1) { read(fd_int, (void *)&reenable, sizeof(int)); // &reenable -> &pending // channel 1 reading value = reg_read(gpio_ptr, GPIO_DATA_OFFSET); if ((value & 0x00000001) != 0) { printf("Interrupt recieved"); } count++; usleep(50000); // anti rebond if(count == 10) flag_end = 1; // the interrupt occurred for the 1st GPIO channel so clear it reg = reg_read(gpio_ptr, GPIO_IRQ_STATUS); if (reg != 0) reg_write(gpio_ptr, GPIO_IRQ_STATUS, 1); // re-enable the interrupt in the interrupt controller thru the // the UIO subsystem now that it's been handled write(fd_int, (void *)&reenable, sizeof(int)); } return ret; } int main(void) { int fd = open("/dev/uio0", O_RDWR); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } int gpio_size = get_memory_size("/sys/class/uio/uio0/maps/map0/size"); /* mmap the UIO devices */ void * ptr_axi_gpio = mmap(NULL, gpio_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); while (1) { wait_for_interrupt(fd,ptr_axi_gpio); } close(fd); exit(EXIT_SUCCESS); } But the issue is that this code is not catching the interrupt. Kindly help me in this. Any suggestion/links are more than welcomed Regards
  8. Best Vivado license option on Zedboards

    Hello I want to buy a Zedboard to evaluate to possibly replacing our existing embedded computer solution (Kontron ETX computer module on a baseboard) with a ZYNQ 7000 based solution. I work at a research institute with a very strong mandate to train students. We will probably put a student on this job to investigate, so we might be able to qualify for the Academic edition of the Zedboard. My question is related to the licenses (vouchers) that come bundled with the zedboards by the various resellers. 1. On the zedboard.org site http://zedboard.org/sites/default/files/product_briefs/PB-AES-Z7EV-7Z020_G-v12.pdf they state: A. (AES-Z7EV-7Z020-G) ZedBoard Commercial Edition (Available Exclusively from Avnet) I have contacted local Avnet rep which stated that this board comes with the Vivado HL Design edition node lock licence valid for 1 year. B. (ZEDBOARD) ZedBoard Academic Edition (Available Exclusively from Digilent) I have contacted digilent which indicate that this board comes with a node locked SDSoC licence valid for 1 year. 2. Looking at other suppliers like Digikey and Mouser (http://www.digikey.com/products/en?keywords=ZEDBOARD) you find -when searching the datasheet- that they provide a voucher for Chipscope licence only. You use webpack with these boards. Now I know that Vivado Webpack should be enough but I want to maximize value by purchasing the most valuable license for our particular application. I would want the student to have maximum flexibility. I think elements that are important are. 1. Good simulation and debugging capabilities i.e. embedded logic analyser, chipscope and a version of ISIM with more features than that shipped with webpack. 2. Good tools for C/C++ software development. We would be looking at integrating EPICS in our solutions. 3. Also access to more IP cores not available in Webpack would also be interesting to evaluate. We would be looking at integrating EtherCAT into our solutions. 4. It would also be nice to do High Level synthesis work (HLS) using C. Please advise me on which resellers' product supply the best/most valuable licensing option. Thank you Chris
  9. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  10. Ways of connecting 2 Zedboard?

    Hello. I was wondering which possible ways there are to connect 2 Zedboard. I read this thread about using an FMC-to-FMC cable and the OP was recommended to look at this. At the moment, I can't afford buying such cables so I was wondering if there are other ways?? I thought of using I2C to communicate one with another (I'd just need to get a few bits from the other Zedboard) but I'm clueless about which connection/pins I should use. Thanks in advance.
  11. XADC working without power supply?

    Hello guys. I was wondering how it is possible that the XADC in the Zedboard does actually convert data even though I didn't feed it with 1.8V power supply? I mean there is a physical pin but I'm not using it, so the XADC shouldn't work but it actually does. How come?Thanks.
  12. zedboard OLED display

    Hi Digilent, zedboard, vivado 2015.4, petalinux 2015.4, /dev/zed_oled, pmodoled-gpio.ko I am working on zedboard to enable onboard-OLED display. First vivado outputs bitstream hardware, then petalinux generates " BOOT.BIN + Image.ub ", finally zedboard bootup by the SD card. " insmod pmodoled-gpio.ko " does bring /dev/zed_oled . However, " cat logo.bin > /dev/zed_oled " has nothing to display. Then I decided to add oled block design in vivado project. I tried two different versions, including tamu https://github.com/ama142/ZedboardOLED-v1.0-IP and Digilent https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodOLED_v1_0 . After making external pin assignment, Vivado / petalinux all functions. However, there is still no outputs on OLED. Please advise how to turn on OLED in petalinux/vivado. Thanks in advance Mike (P.S. OLED by itself works well on OOB package with digilent logo output)
  13. LPC-FMC to FMC connection between ADC & ZEDBOARD

    hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  14. IP core with interrupts

    Hi, Can someone point to me please where can i find a tutorial/explanations how to use an IP core (in vivado) that interrupts the PS in a bare-metal application ? Until now i just created an IP for which I enabled "Interrupt suport"(created another interface for my block - S_AXI_INTR). By default, there is a timer(4 bits) which interrupts ARM in 10 steps. I followed this thread but is for microblaze and uses a axi interrupt controller. I want to link directly to PS because i have no other interrupts in the system. Regards, Mihai
  15. Zedboard

    Hello, I have purchased a zedboard recently. There was SD card (4 Gb ) in it. Now, I want to install GNURadio on this card and to connect this zedboard with a display screen. Please, help me out here... PS: I need GNURadio to run from SD card on zedboard itself (no other host computer) .
  16. Hi, I'm trying to install a module driver in my petalinux rootfs for using on zedboard. I configured an IP core for PL, which has two AXI memory mapped ports (pic1). Now, for using my driver which is responsible for communications with my IP core, i need to know the conversions from phisical addresses to virtual addresses made by kernel. At installation i see just one conversion (S00 is Lite and S01 is Full) : root@avnet-digilent-zedboard-2017_2:/lib/modules/4.9.0-xilinx-v2017.2/extra# insmod driver-mihaiv1.ko [ 1324.279333] <1>Hello module world. [ 1324.282663] <1>Module parameters were (0xdeadbeef) and "default" [ 1324.289030] driver-mihaiv1 43c00000.accHW: Device Tree Probing [ 1324.294839] driver-mihaiv1 43c00000.accHW: no IRQ found [ 1324.299993] driver-mihaiv1 43c00000.accHW: driver-mihaiv1 at 0x43c00000 mapped to 0xe09c0000 In pics you can see the phisical adresses for my IP core. As i see, just the first phisical adress has a virtual conversion <0x43c00000 to 0xe09c0000>. Has anyone met this problem?
  17. Hi, I installed also petalinux 2015.4 (beside 2017.2) in the scope of solveing my problem, but without success. I want to integrate a kernel driver into petalinux rootfs to comunicate with an PL block which has 2 interfaces (lite interface and full interface - both memory mapped). When i created the module into petalinux, i let the code as it was generated..just i overwrote the ".compatible" section with the comptabile section from pl.dtsi(in my case <xlnx,accHW-1.0>) At insmod it doesn't output both conversions (phisical to virtual adresses). It shows just the conversion for the lite interface (0x43c0 0000 to 0xe09a 0000). root@Avnet-Digilent-ZedBoard-2015_4:/lib/modules/4.0.0-xilinx/extra# insmod driv er-mihai.ko [ 95.237408] <1>Hello module world. [ 95.240737] <1>Module parameters were (0xdeadbeef) and "default" [ 95.246938] driver-mihai 43c00000.accHW: Device Tree Probing [ 95.252540] driver-mihai 43c00000.accHW: no IRQ found [ 95.257580] driver-mihai 43c00000.accHW: driver-mihai at 0x43c00000 mapped to 0xe09a0000 What i have to change in driver code to see both conversions ? Or where can i see them ?
  18. U-boot error on kernel load

    Hi, I try to use petalinux 2017.2 to create a linux kernel for running on zedboard. I copied all the files from <petalinux_project_created>/images/linux$ and also <petalinux_project_created>/pre-built/linux/images$ into a fat32 partion on sdcard. At power on, I expected to get automatically into bootloader and just to run the command "run bootcmd" to get into linux OS, but it doesn't. I dowloded the bitstream and the u-boot.elf to get there. In this way i get into the u-boot but i get a strange error ... Zynq> run bootcmd Device: sdhci@e0100000 Manufacturer ID: 74 OEM: 4a60 Name: USD Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.5 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes ** Invalid partition 1 ** I have 2 partions on my sdcard (BOOT - 450MB - FAT32 and ROOTFS-7GB-ext4). Did anyone meet this error? Thanks, Mihai
  19. Hi, I followed UG981 for instalation of a new app in petalinux system. My problem is that i can not find a newer version for this guide. I'm using Petalinux 2017.2 and this guide dates from 3 June 2014. It seems that the structure of a petalinux project has changed alot. I created an app and called it "helloMihai". It seems that my app was created in this path "/project-spec/meta-user/recipes-apps/". This guide says that i should get a path like "<project-root>/components/apps/myapp". mihai@mihai-ThinkStation-P310:~/FPGA/accelerator$ find . -iname "helloMihai" ./build/tmp/sysroots/plnx_arm/sysroot-providers/helloMihai ./build/tmp/sysroots/plnx_arm/pkgdata/helloMihai ./build/tmp/sysroots/plnx_arm/pkgdata/runtime-reverse/helloMihai ./build/tmp/sysroots/plnx_arm/pkgdata/runtime/helloMihai ./build/tmp/deploy/licenses/helloMihai ./build/tmp/stamps/cortexa9hf-neon-xilinx-linux-gnueabi/helloMihai ./build/tmp/work/cortexa9hf-neon-xilinx-linux-gnueabi/helloMihai ./project-spec/meta-user/recipes-apps/helloMihai The real problem is that when i try to build and include my app in root file system, i get an error... mihai@mihai-ThinkStation-P310:~/FPGA/accelerator$ petalinux-build -c rootfs/helloMihai [INFO] building rootfs/helloMihai [INFO] sourcing bitbake INFO: bitbake rootfs/helloMihai Loading cache: 100% |############################################| Time: 0:00:00 Loaded 3235 entries from dependency cache. Parsing recipes: 100% |##########################################| Time: 0:00:01 Parsing of 2447 .bb files complete (2411 cached, 36 parsed). 3237 targets, 224 skipped, 0 masked, 0 errors. ERROR: Nothing PROVIDES 'rootfs/helloMihai'. Close matches: helloMihai Summary: There was 1 ERROR message shown, returning a non-zero exit code. ERROR: Failed to build rootfs/helloMihai Can someone help me with this issue ?
  20. (Not sure if this thread should go in Embedded Linux. If so, please feel free to move it) Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand. Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be: Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this: touch output ./streamread /dev/xillybus_datastream output This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000... Info: I generated the XADC using the wizard so I guess everything is properly instantiated. Tests I've run so far: I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well. Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was. This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high? I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it. Thank you (and sorry for the long post )
  21. Hi, I want to boot a petalinux image on hardware(zedboard) with sd card. I followed this guide, and in page 31 it says that i have to copy the files BOOT.BIN and image.ub into a FAT32 partion on sdcard. I power on the board and linked to it with teraterm. I expect to boot the petalinux image but without success. I set JP9 and JP10 on 3,3V for sdcard boot mode. Can anyone help me ? Regards, Mihai
  22. Connect Zedboard through VirtualBox

    Hi, I want to connect my zedboard to virtual machine (Ubuntu 16.04 64 bit in VirtualBox). When i try to connect throught XMD console to zedboard, it appears that the cable is not connected. Can anyone help me with some hints or advices ?
  23. Hi, I saw here that after the build process i need to get a /tftpboot directory from where i can get the kernel image, rootfile system and dtb file. I use PetaLinux 2017.2 (last version). I also config petalinux to copy final images to tftpboot(pic). It is possible to have been changed the build petalinux structure on last version ? I also run for this folder but i could not find it. sudo find / -type d -iname "tftpboot" Any idea? Regards, Mihai
  24. Hi, At the first time i run the petalinux installer with sudo rights. At build one project i got the error : mihai@mihai-VirtualBox:~/petalinuxOS/accelerator$ petalinux-build [INFO] building project [INFO] sourcing bitbake ERROR: Failed to source bitbake ERROR: Failed to build project webtalk failed:PetaLinux statistics:extra lines detected:notsent_nofile! webtalk failed:Failed to get PetaLinux usage statistics! After searching a little i found in this thread that this problem is generated because i did not install the petalinux as a normal user. I tried to reinstall as a normal user, but i saw in the entire log that the comm "Cannot utime: Operation not permitted" or "Cannot open: File exists" was everywhere: ........................... tar: ./tools/hsm: Cannot utime: Operation not permitted tar: ./tools: Cannot utime: Operation not permitted tar: ./settings.sh: Cannot open: File exists tar: .: Cannot utime: Operation not permitted tar: Exiting with failure status due to previous errors ********************************************* ERROR: Failed to install PetaLinux SDK into "/opt/PetaLinux//." ********************************************* I also set before : mihai@mihai-VirtualBox:~$ source /opt/Xilinx/Vivado/2017.2/settings64.sh Is there anyone who met this problem? Regards, Mihai
  25. LabView Panel VI's for ZedBoard?

    Hello everyone. My name is Shawn and I am new to the Forums. I was wondering if there are any VI's that specifically support the ZedBoard. For example, VI's to load the FPGA code or communicate over the JTAG, or USB ports. Thank you very much in advance, -Shawn