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Found 82 results

  1. Hi everybody, thaks for your time. I'm a new Xilinx user and I'm learning about VHDL language and FPGA. In this opportunity, I want to establish a I2C communication between Zedboard and PmodACL. I'm implementing the tutorial "Getting Started with Digilent Pmod IPs", and I have some doubts: 1) I've installed the "vivado-library-2015.4-3", but when I search the info in board section about Pmod there is nothing: 2) When I click on "Generate Bitstream" I get this error: With this lines: Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 8 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin1_iobuf/IBUF (in pmod_out_pin1_iobuf macro) has no loads. An input buffer must drive an internal load. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin4_iobuf/IBUF (in pmod_out_pin4_iobuf macro) has no loads. An input buffer must drive an internal load. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. I think it's because in the block design I could not open the Pmod corresponding to the Zedboard and then the pin assignment is not elaborated. So, how can i do to import the complete library for Zedboard pmod? Or, which is the order for Pmod pin assignment? Bests reggards, Oscar.
  2. Dear Experts, I have a Zedboard and I am running Petallinux 2015.4, now I want to read and write to file that should be stored on QSPI. I followed this tutorial, http://www.wiki.xilinx.com/Zynq+QSPI+Driver but when I write cat /proc/mtd, it does not show any partitions but my device tree contains the same partitions. Kindly help me in this regard. Regards
  3. Hi, we are using AVNET ZedBoard and we would like to pull out a control signal from our Pmod port. Now the voltage can only reach 2.5V from Jc and Jd port, and reach 0.75V from Ja and Jb port. However, we need a voltage greater than 3V to drive our add-on mux. Is that possible for a PMOD to reach 3V on the ZedBoard? Thank you very much. Angie
  4. Dear Experts I need help regarding interrupt handling using UIO. I am using Vivado 2015.4 and Petalinux 2015.4. The board used is Zedboard. I made the following vivado project attached as image. The interrupts from AXI and Fabric (PL-PS) are enabled. Afterwards i was able to export it as UIO and it shows in /dev as uio0. Now I implemented the following code by following this link: My code is as follows: /* * File: main.c * Author: fss * * Created on August 23, 2017, 12:35 PM */ #include <sys/mman.h> #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include <poll.h> #include <fcntl.h> #include <errno.h> #define GPIO_DATA_OFFSET 0x00 #define GPIO_TRI_OFFSET 0x04 #define GPIO_DATA2_OFFSET 0x08 #define GPIO_TRI2_OFFSET 0x0C #define GPIO_GLOBAL_IRQ 0x11C #define GPIO_IRQ_CONTROL 0x128 #define GPIO_IRQ_STATUS 0x120 unsigned int get_memory_size(char *sysfs_path_file) { FILE *size_fp; unsigned int size; // open the file that describes the memory range size that is based on the // reg property of the node in the device tree size_fp = fopen(sysfs_path_file, "r"); if (size_fp == NULL) { printf("unable to open the uio size file\n"); exit(-1); } // get the size which is an ASCII string such as 0xXXXXXXXX and then be stop // using the file fscanf(size_fp, "0x%08X", &size); fclose(size_fp); return size; } void reg_write(void *reg_base, unsigned long offset, unsigned long value) { *((volatile unsigned long *)(reg_base + offset)) = value; } unsigned long reg_read(void *reg_base, unsigned long offset) { return *((volatile unsigned long *)(reg_base + offset)); } uint8_t wait_for_interrupt(int fd_int, void *gpio_ptr) { static unsigned int count = 0, bntd_flag = 0, bntu_flag = 0; int flag_end=0; int pending = 0; int reenable = 1; unsigned int reg; unsigned int value; // block (timeout for poll) on the file waiting for an interrupt struct pollfd fds = { .fd = fd_int, .events = POLLIN, }; int ret = poll(&fds, 1, 100); printf("ret is : %d\n", ret); if (ret >= 1) { read(fd_int, (void *)&reenable, sizeof(int)); // &reenable -> &pending // channel 1 reading value = reg_read(gpio_ptr, GPIO_DATA_OFFSET); if ((value & 0x00000001) != 0) { printf("Interrupt recieved"); } count++; usleep(50000); // anti rebond if(count == 10) flag_end = 1; // the interrupt occurred for the 1st GPIO channel so clear it reg = reg_read(gpio_ptr, GPIO_IRQ_STATUS); if (reg != 0) reg_write(gpio_ptr, GPIO_IRQ_STATUS, 1); // re-enable the interrupt in the interrupt controller thru the // the UIO subsystem now that it's been handled write(fd_int, (void *)&reenable, sizeof(int)); } return ret; } int main(void) { int fd = open("/dev/uio0", O_RDWR); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } int gpio_size = get_memory_size("/sys/class/uio/uio0/maps/map0/size"); /* mmap the UIO devices */ void * ptr_axi_gpio = mmap(NULL, gpio_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); while (1) { wait_for_interrupt(fd,ptr_axi_gpio); } close(fd); exit(EXIT_SUCCESS); } But the issue is that this code is not catching the interrupt. Kindly help me in this. Any suggestion/links are more than welcomed Regards
  5. AXI DMA

    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. https://github.com/mstuehn/dma_proxy Any help is appreciates Best regards,
  6. Zybo tutorial help

    i currently have a project where i need to produce a tone from a zybo board and to familiarise myself with the board i downloaded the pdf from http://www.zynqbook.com/download-tuts.html and the zip files but and i do the tutorials step for step but when i try to run the programme on the board nothing happens im using vivado 2017.1 i have the ports set to 115200 baud when i import the c code i get a warning from xparamaters.h i asked my project manager and they said its because im not using costraints but the turtorial specifically mentions not using constraints can anyone tell me what am i doing wrong despite the fact im doing the tutorial step for step?
  7. Petalinux Kernel module

    Hi I want to transfer data from PL to PS via DMA. I am using zedboard. I am using petalinux in the PS. i have created a module for the DMA called "axidma". i have a header file in the module named axidma.h where i have defined some macros. axidma.h and axidma.c are in the same directory. Now i want to use those macros in user space applicatiion but i cannot access them. I know it is possible by changing the makefile of the module but i am not an expert in makefiles so i dont know how to do that. Any help will be appreciated
  8. Hello, is the ADC of Zedboard able to sample negative signals? And what are the specifications of the ADC built in? Thank You! Best regards
  9. Using Pmod of PS-Side of Zedboard

    Hello, I am trying to generate a Digital Output by using the Zynq Processing System. I tought using the Pmod would be easy to handle but I am already failing to design the hardware to activate the Pmod MIO. Do you know a (or similar) tutorial for that? Can you give some advises how to realize it? Thank You! Best regards
  10. Hello, is it possible to sample an external analog signal using the XADC? Or do I need the AMS101 Eval-Card for that? I'm using the Sony XC-HR50 analog Camera (datasheet: https://pro.sony.com/bbsc/ssr/product-XCHR50/ ), which has a CCD Sensor. I am very new to Zedboard and trying do save the picture of the camera. Thank you, kind regards The Video Output is shown below:
  11. Dear MembersI am working on Petalinux 2015.4 and ZedBoard, I am trying to connect a CF Card through USB OTG, but the device doesnot gets registered and won't show up in /dev and I cannot mount it. Kindly help me in this regard.Regard
  12. Vmodcam problems

    Hi, I am using vmodcam and have problem with image resolution and bad pixels. I have microZed 7010 board and I/O carrier and try to send image via Ethernet. First problem is, I set all the register values mentioned in the rm (https://reference.digilentinc.com/_media/vmodcam/vmodcam_rm.pdf) to get image with resolution 1600x1200 px. Unfortunately I got image containing 4 frames with resolution 800x600 px (attachment: bad_res_image.jpg). Before logging image I saw values in these registers via I2C and everything in the register is set as in the rm. Do you have any idea what is wrong? Second problem is more serious. In this link I send the results when I show only 800x600 px of the image (https://imgur.com/a/nmviB). - in 70% of cases the image I get is wrong (picture 3, 4 in the link) - in 10% of cases the image I get is shifted in some places and but we can recognize the shape (picture 5 in the link) - in 20% of cases I get image which is OK (picture 1, 2 in the link) But in 100% of cases my image have bad pixels. I would really appreciate any help or even only a hint. Thank you in advance! Best regards czajak
  13. Dear Experts I am using Petalinux 2015.4 and Zedboard. I am reading a GPIO which is supposed to go from 0 to 1 and in commandline, I can see that it happens. But when I execute it in the code, the value always remain 0 as initial value is 0. My code is as follows: int number=-1; unsigned char error = 0; int fd_done; //Export GPIO fd_done = open("/sys/class/gpio/export", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Export Failed\n\r"); #endif error=1; } write(fd_done,"903",3); close(fd_done); //Set GPIO as input fd_done = open("/sys/class/gpio/gpio903/direction", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Direction Failed\n\r"); #endif error=1; } write(fd_done,"in",2); close(fd_done); char value; fd_done = open("/sys/class/gpio/gpio903/value", O_WRONLY); lseek(fd_done, 0, SEEK_SET); read(fd_done, &value, 8); printf("Done Value: \t %d \n",value); close(fd_done); fd_done = open("/sys/class/gpio/unexport", O_WRONLY); write( fd_done,"903",3); close(fd_done); return number;
  14. Dear Expert I am working on Petalinux 2015.4 and Zedboard. I want to have a contagious 4 MB block of DDR to communicate with PL and have the physical address of the its Base. -Can I have this much memory allocated? -How can I get physical address of the memory? Regards
  15. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  16. Best Vivado license option on Zedboards

    Hello I want to buy a Zedboard to evaluate to possibly replacing our existing embedded computer solution (Kontron ETX computer module on a baseboard) with a ZYNQ 7000 based solution. I work at a research institute with a very strong mandate to train students. We will probably put a student on this job to investigate, so we might be able to qualify for the Academic edition of the Zedboard. My question is related to the licenses (vouchers) that come bundled with the zedboards by the various resellers. 1. On the zedboard.org site http://zedboard.org/sites/default/files/product_briefs/PB-AES-Z7EV-7Z020_G-v12.pdf they state: A. (AES-Z7EV-7Z020-G) ZedBoard Commercial Edition (Available Exclusively from Avnet) I have contacted local Avnet rep which stated that this board comes with the Vivado HL Design edition node lock licence valid for 1 year. B. (ZEDBOARD) ZedBoard Academic Edition (Available Exclusively from Digilent) I have contacted digilent which indicate that this board comes with a node locked SDSoC licence valid for 1 year. 2. Looking at other suppliers like Digikey and Mouser (http://www.digikey.com/products/en?keywords=ZEDBOARD) you find -when searching the datasheet- that they provide a voucher for Chipscope licence only. You use webpack with these boards. Now I know that Vivado Webpack should be enough but I want to maximize value by purchasing the most valuable license for our particular application. I would want the student to have maximum flexibility. I think elements that are important are. 1. Good simulation and debugging capabilities i.e. embedded logic analyser, chipscope and a version of ISIM with more features than that shipped with webpack. 2. Good tools for C/C++ software development. We would be looking at integrating EPICS in our solutions. 3. Also access to more IP cores not available in Webpack would also be interesting to evaluate. We would be looking at integrating EtherCAT into our solutions. 4. It would also be nice to do High Level synthesis work (HLS) using C. Please advise me on which resellers' product supply the best/most valuable licensing option. Thank you Chris
  17. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  18. Ways of connecting 2 Zedboard?

    Hello. I was wondering which possible ways there are to connect 2 Zedboard. I read this thread about using an FMC-to-FMC cable and the OP was recommended to look at this. At the moment, I can't afford buying such cables so I was wondering if there are other ways?? I thought of using I2C to communicate one with another (I'd just need to get a few bits from the other Zedboard) but I'm clueless about which connection/pins I should use. Thanks in advance.
  19. XADC working without power supply?

    Hello guys. I was wondering how it is possible that the XADC in the Zedboard does actually convert data even though I didn't feed it with 1.8V power supply? I mean there is a physical pin but I'm not using it, so the XADC shouldn't work but it actually does. How come?Thanks.
  20. zedboard OLED display

    Hi Digilent, zedboard, vivado 2015.4, petalinux 2015.4, /dev/zed_oled, pmodoled-gpio.ko I am working on zedboard to enable onboard-OLED display. First vivado outputs bitstream hardware, then petalinux generates " BOOT.BIN + Image.ub ", finally zedboard bootup by the SD card. " insmod pmodoled-gpio.ko " does bring /dev/zed_oled . However, " cat logo.bin > /dev/zed_oled " has nothing to display. Then I decided to add oled block design in vivado project. I tried two different versions, including tamu https://github.com/ama142/ZedboardOLED-v1.0-IP and Digilent https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodOLED_v1_0 . After making external pin assignment, Vivado / petalinux all functions. However, there is still no outputs on OLED. Please advise how to turn on OLED in petalinux/vivado. Thanks in advance Mike (P.S. OLED by itself works well on OOB package with digilent logo output)
  21. LPC-FMC to FMC connection between ADC & ZEDBOARD

    hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  22. IP core with interrupts

    Hi, Can someone point to me please where can i find a tutorial/explanations how to use an IP core (in vivado) that interrupts the PS in a bare-metal application ? Until now i just created an IP for which I enabled "Interrupt suport"(created another interface for my block - S_AXI_INTR). By default, there is a timer(4 bits) which interrupts ARM in 10 steps. I followed this thread but is for microblaze and uses a axi interrupt controller. I want to link directly to PS because i have no other interrupts in the system. Regards, Mihai
  23. Zedboard

    Hello, I have purchased a zedboard recently. There was SD card (4 Gb ) in it. Now, I want to install GNURadio on this card and to connect this zedboard with a display screen. Please, help me out here... PS: I need GNURadio to run from SD card on zedboard itself (no other host computer) .
  24. Hi, I'm trying to install a module driver in my petalinux rootfs for using on zedboard. I configured an IP core for PL, which has two AXI memory mapped ports (pic1). Now, for using my driver which is responsible for communications with my IP core, i need to know the conversions from phisical addresses to virtual addresses made by kernel. At installation i see just one conversion (S00 is Lite and S01 is Full) : root@avnet-digilent-zedboard-2017_2:/lib/modules/4.9.0-xilinx-v2017.2/extra# insmod driver-mihaiv1.ko [ 1324.279333] <1>Hello module world. [ 1324.282663] <1>Module parameters were (0xdeadbeef) and "default" [ 1324.289030] driver-mihaiv1 43c00000.accHW: Device Tree Probing [ 1324.294839] driver-mihaiv1 43c00000.accHW: no IRQ found [ 1324.299993] driver-mihaiv1 43c00000.accHW: driver-mihaiv1 at 0x43c00000 mapped to 0xe09c0000 In pics you can see the phisical adresses for my IP core. As i see, just the first phisical adress has a virtual conversion <0x43c00000 to 0xe09c0000>. Has anyone met this problem?
  25. Hi, I installed also petalinux 2015.4 (beside 2017.2) in the scope of solveing my problem, but without success. I want to integrate a kernel driver into petalinux rootfs to comunicate with an PL block which has 2 interfaces (lite interface and full interface - both memory mapped). When i created the module into petalinux, i let the code as it was generated..just i overwrote the ".compatible" section with the comptabile section from pl.dtsi(in my case <xlnx,accHW-1.0>) At insmod it doesn't output both conversions (phisical to virtual adresses). It shows just the conversion for the lite interface (0x43c0 0000 to 0xe09a 0000). root@Avnet-Digilent-ZedBoard-2015_4:/lib/modules/4.0.0-xilinx/extra# insmod driv er-mihai.ko [ 95.237408] <1>Hello module world. [ 95.240737] <1>Module parameters were (0xdeadbeef) and "default" [ 95.246938] driver-mihai 43c00000.accHW: Device Tree Probing [ 95.252540] driver-mihai 43c00000.accHW: no IRQ found [ 95.257580] driver-mihai 43c00000.accHW: driver-mihai at 0x43c00000 mapped to 0xe09a0000 What i have to change in driver code to see both conversions ? Or where can i see them ?