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Found 6 results

  1. so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc fil
  2. I would like to integrate PMOD NIC100 with Microzed board with Zynq 7020 running on linux. I have a SPI interface routed through the PL logic. Are there any IP that can be directly imported to Vivado for this ? OR Are there any drivers that can be installed on the linux ? Please suggest.
  3. Hi all, Maybe it's just a small detail that is missing but I don't know how to solve it exactly. I’m trying to communicate my laptop with my ZedBoard but for some reason, it suddenly stops. I follow the procedure indicated in instructions included with the ZedBoard package and are also indicated in this tutorial. I download the USB to UART adapter driver (controller version 3.13.0.59) by Cypress which controls the USB serial port (in this case COM9). The device is identified as Cypress-USB2UART-Ver1.0G. The settings form COM9 are like the figures. When I turn on the ZedBoard wi
  4. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here
  5. I'm using Vivado 2019 and a Zedboard, trying to implement "HelloWorld" in PS and output "Hello World" at PC terminal.but it doesn't work. usb-uart and usb-jtag is connected with PC (Win10) i'm using mio-46,47 to uart0 please help me... my step: 1. vivado open block design > HDL wrapper 2. run implementation 3.Export Hardware 4. launch SDK > new application project 5. open putty for monitor (COM4, speed is 115200) 6. SDK run configuration and the setting as following > Run 7. run result as following
  6. Hello While I was working on ZedBoard with USB-JTAG, the USB port suddenly broke apart. When I contact the USB port pins with the board pins, I can still do stuff, but I want this port to be fixed to the board. So I requested RMA to my seller but she told me that the warranty period is over and guided me to post a question in this forum. I bought the board on Oct 05, 2018. Any way to get this broken port fixed?