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Found 9 results

  1. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &
  2. Hello there, Can i use file systems in SDK? when i tried running simple example(shown below) on ARM(in ZED board), it is not giving me any results. Can someone please tell me why it is so? file.c
  3. want to buy ZEDBOARD ZYNQ-7000 ARM/FPGA SOC. Will RTL code provided with the board? what do i expect to get? Thanks,
  4. Hello, I am using Zed board 7000. I want to do Image Processing or basic computation in Zed board on PL side using FPGA. I was a bit confused to start either with a Linux image(PetaLinux or Xillinux) or directly through the Vivado software. Is it possible to do any computation or Image Processing on the PL side using ARM processor only to interface the peripherals(I don't want the computation to be done on the ARM processor). Kindly provide any reference link or tutorial which can address my queries. Thanks in advance. ---Nikith--
  5. Nikith

    Petalinux or Xillinux

    Hi, Which one is better Petalinux or Xillinux? If yes, Why? Thanks in advance. --Nikith--
  6. Hi there, I get this error when I run the C simulation in HLS to implement on zed board. I know that this error occurs when classes or class member functions are set as the top-level for synthesis. But i am not able to figure out where exactly i am going wrong. Can someone guide me here.?
  7. Hi there, I have a zed board and i want store data into DDR3 for my application. The data is in .txt file. I stored it. But when i am reading the data , its giving the wrong values. Can someone help me? firstly, Is it correct what i am doing? thanks in advance
  8. Hello there, I have developed an image processing algorithm using the system generator and Generated the HDL netlist. Now i need to send the image file to the Verilog code generated, and compute the output and measure the time. Can anyone please help me in understanding how i should, input the image, get the output and then measure the time of execution on ZED board? Thanks in advance.
  9. Good Day, I just purchased and received the Zed board from you folks. According to the product page, I'm supposed to have a voucher for one of the non-free versions of Vivado. Although the CD was shipped, I couldn't find a voucher. Where may I acquire it? Also, my understanding is that this license is device locked. So, I've been using Vivado free edition with my Nexys4 DDR. In order to keep using that board, am I going to need to have a separate install of Vivado - i.e. one free for my Nexys4 DDR and one for the Zed board? Thanks, Dave