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Found 3 results

  1. Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description> <port_maps> <port_map logical_port="clk" physical_port="clk" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> Which allows one to click and drag "System Clock" from the board tab into the block design and gives you a clocking wizard with a single-ended clock. I want to be able to do the exact same thing, except instead of spawning a clocking wizard with a single-ended clock, it spawns a clocking wizard with a differential clock, like this: Here is my failed attempt at creating this interface: I used "xilinx.com:signal:diff_clock_rtl:1.0" instead of "xilinx.com:signal:clock_rtl:1.0" and added another port map for the p/n signals. <interface mode="slave" name="sys_clock" type="xilinx.com:signal:diff_clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Double-Ended 100MHz oscillator used as system clock on the board that don't work none good</description> <port_maps> <port_map logical_port="CLK_P" physical_port="clk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="clk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_n"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> and I added the following pins to my pin file: <?xml version="1.0" encoding="UTF-8" standalone="no"?> <part_info part_name="xc7a200tffg1156-2"> <pins> <pin index="00" name ="clk_p" iostandard="LVCMOS25" loc="AG29" /> <pin index="01" name ="clk_n" iostandard="LVCMOS25" loc="AG30" /> Which gives me this message: "'System Clock' board component cannot be connected because no possible options to connect." when I try to click and drag system clock into the design: Do I need to edit the preset file, or is the syntax for my interface definition incorrect, or am I missing something else entirely? Any help is greatly appreciated. Thanks in advance
  2. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml
  3. DoogieTech

    Arty Board File

    Is there a .xml file available for vivado 14.4 and earlier for the Arty? Thanks!