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Hi, I have a ZEDBOARD which I want to interface it to an analog input signal and see the sinusoidal output. i'm following lab 3 tutorial by Adam Taylor. So, as for the first step, I tried to connect the signal generator to Vn and Vp. I expected to see the sinusoidal shape of the voltage in XADC dashboard (XADC wizard demo). and also set the ENABLE_ALL_AUXILIARY_CHANNELS check mark, which will include Vp/Vn. I set the function generator to frq 50Hz and amplitude 400-600 vpp, or DC also I applied and checked the signal on the dashboard and serial oscilloscope both. But, the board produces no reaction and the Vp_Vn channel still gives an uneven sine wave or i guess its noise or something else. I tried so many times but still i'm stuck at this point . Could anyone suggest any solution or PoW ?
Hi All, I am beginner in FPGA world. I am trying to learn how to work with Vivado IP Integrator. When i try to launch my firstProj on Launch on Hardware(System Debugger) I am getting a such kind of issue: make all Building file: ../main.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"main.o" -I../../firstproj_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"main.d" -MT"main.o" -o "main.o" "../main.c" Finished building: ../main.c Building target: firstproj.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../firstproj_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "firstproj.elf" ./main.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: firstproj.elf section `.heap' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' makefile:35: recipe for target 'firstproj.elf' failed /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 1168 bytes collect2: error: ld returned 1 exit status make: *** [firstproj.elf] Error 1 19:49:21 Build Finished (took 335ms) I try to search on google but cannot to find an answer. Can someone help to understand the reason? I am thiinking that this may be some tool setup issue. Thanks!