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Found 71 results

  1. I had left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. Though, the computer's device manager shows that something is plugged in. Yet, adept and vivado are unable to recognize that a device is connected - on vivado I was planning to restore the board to it's default setting using a .bin file but received the following error message: ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Common 17-39] 'open_hw_target' failed due to earlier err. I used a voltmeter to test the voltage across the on/off switch and was getting around 3.3V but now get 0.003V. When I tested the switches that control the on-board LEDS, the also produced around 0.003V. Please help.
  2. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_consulting/Digilent_Xilinx/Zybo_eval_Xilinx_Zynq/Example_Prjs/Zybo-Z7-20-DMA-2018.2-1/vivado_proj/Zybo-Z7-20-DMA.runs/system_processing_system7_0_0_synth_1/.Xil/Vivado-7036-Rafi-GamePC//incrSyn/system_processing_system7_0_0.genomesNotDumped": no such file or directory Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1045.969 ; gain = 379.242 INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 101 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Vivado Synthesis failed INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 07:07:59 2020... ============================ Vivado version: 2018.2
  3. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  4. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  5. tomii


    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting around my home "lab," I've got a few Opal Kelly boards (XEM3001, XEM3005, and a couple others) - I love the FrontPanel system they've developed. I've also got an Arty (35T) and now a Cora (low-end Zedboard), and I'm itching to learn some stuff there. I also do a fair amount of bare-metal embedded when I need to (e.g. Atmel/Microchip microcontrollers), and have also recently been doing some stuff with embedded Linux on the pi platform. Lastly, let's talk about the registration process. Jimminy Christmas, it took me and another engineer 8 tries to get validated! Holy cow, am I st00pid, or what? -Tom
  6. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
  7. Dear sir, I am using xilinx FFT 9.0 IP core in Vivado 15.2 for my application, I am computing 512 point IFFT with cyclic prefix using this IP core but output is not coming correctly. Although most of the output samples are correct but some samples are changing drastically. I am using this IP core in real time mode and giving 512 complex symbol at the input of core on every clock after s_axis_data_tvalid and s_axis_data_tready becomes high. Earlier I have used xilinx FFT 7.1 IP core in ISE14.6 which working fine with same settings and same input data. Kindly help me to debug this IP core
  8. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is always the same -- it intermittently disconnects and fails. The amber LED does however stay lit. In Device Manager I am able to see the FTDI UART. I did also see it enumerate as a Microsoft BallPoint Mouse -- whatever that is. With this exact same setup, PC, Vivado, USB cables, etc, I have been programming the Zybo Z7-20 and the Arty boards with several designs without any such issues. Please let me know if I missed anything and what are the next steps in getting the board replaced or fixed. Thanks.
  9. Wyorin


    I have developed a test system using a Xilinx Spartan 6 and the Digilent JTAG-SMT2 programming module. I can program the device OK but if I include an Chipscope ILA and run the analyser the ILA is not found. I know that the ILA is in the build because I have looked for it using ISE14.7 FPGA Editor. I have turned the JTAG clock speed right down to 125 kHz, but still no joy. Any thoughts?
  10. Xilinx Tools FPGA and ARM Coding? How does one program the newer boards with HDL and C coding on one platform? Do the tools support both processor and VHDL or Verilog? I don't see the big picture here. I am working the Spartan 3 and 6 designs. I would like to move into the Artix 7 at some point. I need a working platform for USB 3.0 and Ethenet 1 G. Phil
  11. I'm trying to communicate with a Digilent JTAG-SMT1 on an older Xilinx KC705 from a Raspberry Pi 3 and I've successfully been able to communicate with it via cmd line. Now I want to convert the 2-wire demo to a 4-wire demo since the SMT1 can only support 4-Wire JTAG. The only problem is that I've had a hard time understanding what the difference between the two is. I just need a push in the right direction since I've gone through the API trying to understand it and I've made very little progress. Thank you for your time.
  12. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  13. Hello Community, I am a newbie and am using Xilinx Vivado 2018.1. I have a project with Kintex 7. I want to connect an external FIFO ( 72T18125L4 ) to Kintex 7 and I want to implement an interface in Kintex 7 to communicate with this FIFO. Please give me the idea! Sorry if I posted in wrong place! :( Thank you very much! Best regards, Charlie.
  14. Hello Digilent Community, I am working on a image processing project and was wondering if anyone had advice or could point me in the right direction. I have tried following some tutorials and example projects, but I am still trying to wrap my head around Xilinx Vivado and SDK. The project really shouldn't be very difficult, I think I am just missing some information or the best way to go about doing it. For the project I am using the Zybo z7-20 development board and want to save two images to an SD card. The two pictures are black and white frames from a video just seconds apart, so there is only slight change in the frames themselves. I want to compare the two frames and output either a black and white image of the change in pixels or a binary file of '0' being an unchanged pixel and '1' being a change in the pixel. MATLAB has the 'Computer Vision System Toolbox' 'Tracking Cars Using Foreground Detection' Simulink example that is similar to what I want to do on the Zybo z7-20 FPGA. The following figure show the original video (right) with blob detection (the green square) and the binary output image of the change in pixels in the foreground (left). I want to use the Zynq Processor and write C code to do the analysis, but I haven't found a clear way to access the SD card from the Xilinx SDK. The following figure is of my current Block Design with only the Zynq Processor as well as some GPIO to test. I am still researching and looking at examples to compare, but wanted to see if the community had any pointers or if someone has done this before. I am a college student and I have been really interested FPGA's and digital design for the past 6-9 months, but I have mainly written my own Verilog code and haven't worked with block design or running C code on any of my designs. Any comments or suggestions would be great. Thanks!
  15. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the desired output but when I run the same through a program created on the host OS that is supposed to communicate with the PL it does not return a desired output or anywhere near it. I am attaching the IP core file, testbench file created in Vivado HLS and the C++ program running on the PS for communicating with the IP. Thank you in advance. core.cpp tb_core.cpp coprocessing.cpp
  16. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  17. I'm trying to boot a Zedboard using a SD card, and it fails. The Power good LED is on, but the 'Done' light remains off. I tried 4 different SD cards (all UHS-I), but later read that UHS-I cards aren't supported, so I'm using a non-UHS card and it still fails to boot. MIO6:2 headers are '01100', which is the SD card boot configuration. I've also shorted JP6 on the board. VADJ is at 1.8V The board boots successfully from QSPI - the blue LED and 4 red LEDs come on. I formatted the SD cards using both: the official SD Card Formatter & Windows 10's inbuilt 'Format' Then I copied the 5 files from the Out-of-box Demo on Digilent's website: I've also tried the 'zedboard_oob_design' from the Avnet forums, and the Analog Devices images from their website - and the board still fails to boot. I've tried the SD cards on another Zedboard, and it fails to boot on that one as well. The UART doesn't print anything (115200, 8N1) either. Is there anything I'm forgetting to check? Does the SD card require a specific format, sector size, partitions etc?
  18. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben
  19. Connecting Intel (Altera) and Xilinx worlds with a cheap cable. I've been doing FPGA development using Altera and Xilinx development tools for many years now. This has produced a lot of years long itches that I've found hard to make go away. Generally, these irritations are caused by obstacles thrown in my way by vendors wanting get money out me. It's really hard to find inexpensive Altera based development boards with an Ethernet PHY not connected to an ARM PS, or with a decent UART port or any useful USB port. However, you can find ways to connect Altera based development boards to ADC/DAC devices with reasonable performance. In the Xilinx world it's the other way around. Both vendors have made playing with transceivers very difficult, especially for the non-premium devices. Both vendors try to use their soft-processor based development flow as the only way to do anything useful with their development boards. The HSMC has long been the standard IO interface providing a reasonable number of IO for both low speed and high speed uses. But try and find a reasonably priced Xilinx development board with an HSMC connector. For too many years the 8 signal PMOD has been the only IO available in the Xilinx world until recently when boards with an FMC connector have become available. Recently, expensive Altera boards with an FMC connector have also become available. So, I have a lot of hardware that can do a lot of things... except what I want. What to do... what to do... Recently, I released an Ethernet test tool to the Digilent Project Vault. If view counts are any measure there hasn't been much interest. I've recently make a demonstration project that resolves a few of the previously mentioned itches. Below is a brief description. The project connects my ATLYS board to two channels of 100 MHz ADC and DAC interfaces. The ALTYS uses the high speed USB 2.0 Adept interface to connect to a C program for downloading DAC waveforms to and upload ADC samples from the DDR2. DAC waveforms can be of arbitrary length. All of this data goes through the ATLYS Ethernet PHY to an Altera Cyclone V GT based development board with 2 HSMC connectors and the rare Ethernet PHY - FPGA fabric connections. One of the HSMC connectors has a Terasic DDC board with 2 250 MHz DACs and 2 150 MHz ADCs. At best Gigabit Ethernet supports 125 million bytes/s full duplex data rates... but the good news is that this is, unlike USB, a sustainable rate with very low latencies. Currently, the project runs all 4 converters at a 100 MHz sample rate. The sample rates supported through the Ethernet cable are 25 MHz. DAC samples from the ATLYS use 4X interpolating filter in the Cyclone FPGA to create 100 MHz samples. ADC samples are decimated to 25 MHz sampling rates. DAC data is sourced from 2 16 KBx16 block ram DPRAM waveform buffersi a ping-pong arrangement so that I can write new waveform data without disturbing the DAC outputs. Whenever the read pointer crosses from one half of the buffer to the other half the Cyclone sends an ADC packet to the ATLYS with 8192 samples. The start of the packet is used as a synchronizing signal to the ALTYS to know when to send the DAc packet. The Ethernet PHYs transfer 100 million bytes/s for DAc waveforms longer than 16384 samples continuously. That's the overview. Why bother to post this? I'm not the only one with an itch problem. Hopefully, this project will spark some interesting solutions to their problems. I've provided 2 pictures to show what's going on. In both CH1 and CH2 are the DAC outputs. CH3 is the ADC packet and CH4 is the DAC packet. Notice the latency bewteen the packets in the blowup image.
  20. Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable . Best, ATIF JAVED
  21. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  22. Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  23. Hello! I'm using an Arty-S7 with a PMODOLED. I want to draw several rectangles on the little display, but the example design seems to delete the previous rectangle when I add a new one. Is there some magic to display multiple rectangles or do I need to dig deeper and hack on OledGrph.c? Thanks! Craig
  24. Hi There, I'm using an Arty-S7 board and am connecting PMODOLEDs to all 4 PMOD connecters (JA, JB, JC, JD). The example that comes with the driver only talks to the PMOD connected to JA, and it works like a champ. Looking at the code and header files, though, I'm not seeing how to talk to the other PMODs. What should I change to talk to the PMODOLEDs on JB, JC or JD. Be gentle, I'm really a hardware guy and using this to learn a little more about C-programming and to that end, the less amount of hacking needed the better. Thanks! Craig
  25. Hi, I've recently bought a Zybo z7010 board and had a go at running the example given here: The bitstream was generated successfully as expected but when I load the application on to the Zynq PS, I observe that: None of the LEDs are lit when the corresponding buttons are flicked. No message is displayed on the UART console when any of the switches are pressed. Can anyone provide some hints on how would I go about debugging the issue? Some info w.r.t my build environment: Bitstream generated using Vivado 2016.4 (Windows 10) Power source: wall (JP7 set to Wall) JP5 set to JTAG. Cable: simple USB cable which came with my smartphone. (When JP5 is set to QSPI, I can see u-boot booting a preloaded busybox image so the cable seems to be working fine.) Please advise. Regards, ahmrah01