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  1. Hello Everyone, I am newbie to Xilinx Platform, please provide your suggestion. > Platform: Xilinx SDx 2019.1 Board: Zedboard Host machine: Ubuntu > I have a general question, when a C++ program executes with good result in one platform, but good results are not obtained while executing the same program in Xilinx SDSoC platform without build errors and implemented on zedboard. > In my case, Acquisition program in C++ works perfect in Qt Creator Application with incomming.bin file, signals are acquired. But while implementing and
  2. I had left my board connected to my laptop and power to the board was abruptly cut off when the laptop died. I tried to connect the board to a different computer and realized that it no longer turned on. Though, the computer's device manager shows that something is plugged in. Yet, adept and vivado are unable to recognize that a device is connected - on vivado I was planning to restore the board to it's default setting using a .bin file but received the following error message: ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292AA77E6A. Check cable
  3. Hello, I bought the Zybo-Z7-20 eval board. I downloaded the DMA project from repository and it ran fine in the EDK. So, far so good. However, when I started to re-run synthesis, there were error in the synthesis as to could not synthesize the Zynq part. Below is the error message from the synth log. I would appreciate anyone noticing this error showing how to get past it. Seems like I am missing some setup files or folder, not sure what .... ============================ Near the end of Error Log: ============================ couldn't open "i:/Rafi/Dropbox/Engr_con
  4. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  5. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Ras
  6. tomii

    Howdy

    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting
  7. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
  8. Dear sir, I am using xilinx FFT 9.0 IP core in Vivado 15.2 for my application, I am computing 512 point IFFT with cyclic prefix using this IP core but output is not coming correctly. Although most of the output samples are correct but some samples are changing drastically. I am using this IP core in real time mode and giving 512 complex symbol at the input of core on every clock after s_axis_data_tvalid and s_axis_data_tready becomes high. Earlier I have used xilinx FFT 7.1 IP core in ISE14.6 which working fine with same settings and same input data. Kindly help me to debug this IP core
  9. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is alwa
  10. Wyorin

    JTAG-SMT2

    I have developed a test system using a Xilinx Spartan 6 and the Digilent JTAG-SMT2 programming module. I can program the device OK but if I include an Chipscope ILA and run the analyser the ILA is not found. I know that the ILA is in the build because I have looked for it using ISE14.7 FPGA Editor. I have turned the JTAG clock speed right down to 125 kHz, but still no joy. Any thoughts?
  11. Xilinx Tools FPGA and ARM Coding? How does one program the newer boards with HDL and C coding on one platform? Do the tools support both processor and VHDL or Verilog? I don't see the big picture here. I am working the Spartan 3 and 6 designs. I would like to move into the Artix 7 at some point. I need a working platform for USB 3.0 and Ethenet 1 G. Phil
  12. I'm trying to communicate with a Digilent JTAG-SMT1 on an older Xilinx KC705 from a Raspberry Pi 3 and I've successfully been able to communicate with it via cmd line. Now I want to convert the 2-wire demo to a 4-wire demo since the SMT1 can only support 4-Wire JTAG. The only problem is that I've had a hard time understanding what the difference between the two is. I just need a push in the right direction since I've gone through the API trying to understand it and I've made very little progress. Thank you for your time.
  13. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS
  14. Hello Community, I am a newbie and am using Xilinx Vivado 2018.1. I have a project with Kintex 7. I want to connect an external FIFO ( 72T18125L4 ) to Kintex 7 and I want to implement an interface in Kintex 7 to communicate with this FIFO. Please give me the idea! Sorry if I posted in wrong place! :( Thank you very much! Best regards, Charlie.
  15. Hello Digilent Community, I am working on a image processing project and was wondering if anyone had advice or could point me in the right direction. I have tried following some tutorials and example projects, but I am still trying to wrap my head around Xilinx Vivado and SDK. The project really shouldn't be very difficult, I think I am just missing some information or the best way to go about doing it. For the project I am using the Zybo z7-20 development board and want to save two images to an SD card. The two pictures are black and white frames from a video just seconds apart, so
  16. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the d
  17. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  18. I'm trying to boot a Zedboard using a SD card, and it fails. The Power good LED is on, but the 'Done' light remains off. I tried 4 different SD cards (all UHS-I), but later read that UHS-I cards aren't supported, so I'm using a non-UHS card and it still fails to boot. MIO6:2 headers are '01100', which is the SD card boot configuration. I've also shorted JP6 on the board. VADJ is at 1.8V The board boots successfully from QSPI - the blue LED and 4 red LEDs come on. I formatted the SD cards using both: the official SD Card Formatter & Windows 10's inbuilt 'Fo
  19. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my
  20. Connecting Intel (Altera) and Xilinx worlds with a cheap cable. I've been doing FPGA development using Altera and Xilinx development tools for many years now. This has produced a lot of years long itches that I've found hard to make go away. Generally, these irritations are caused by obstacles thrown in my way by vendors wanting get money out me. It's really hard to find inexpensive Altera based development boards with an Ethernet PHY not connected to an ARM PS, or with a decent UART port or any useful USB port. However, you can find ways to connect Altera based development boards to ADC/
  21. Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable .
  22. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PA
  23. Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  24. Hello! I'm using an Arty-S7 with a PMODOLED. I want to draw several rectangles on the little display, but the example design seems to delete the previous rectangle when I add a new one. Is there some magic to display multiple rectangles or do I need to dig deeper and hack on OledGrph.c? Thanks! Craig
  25. Hi There, I'm using an Arty-S7 board and am connecting PMODOLEDs to all 4 PMOD connecters (JA, JB, JC, JD). The example that comes with the driver only talks to the PMOD connected to JA, and it works like a champ. Looking at the code and header files, though, I'm not seeing how to talk to the other PMODs. What should I change to talk to the PMODOLEDs on JB, JC or JD. Be gentle, I'm really a hardware guy and using this to learn a little more about C-programming and to that end, the less amount of hacking needed the better. Thanks! Craig