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Showing results for tags 'xilinx fpga'.
Dear all Please help in accessing ethernet port of Atlys FPGA board. Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it. please reply if anybody has done that. -- Gopal krishna
We are using a JTAG-SMT2-NC for JTAG access through one of our daughter cards. This has worked in the past using KU115 and VU5P FPGAs paired with a Zynq. However now the VU9P the JTAG chain is unstable in Adept and Vivado hardware manager where most of the time it will not correctly scan the chain and give device IDs that do not match with devices in the chain. Is there an incompatibility with the JTAG-SMT2-NC and the VU9P FPGAs? Thanks, David
Hi, I was looking to know what CYINIT is in CARRY4 block and it's role? I assume the CI is the carry in from previous cascade, but not sure. Any idea on this? I use Xilinx 7-series device in Vivado 2019.1, we can refer UG953 (page.290) for CARRY4 block. Thank you,