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Found 7 results

  1. Mell

    Vivado CLOCK_DEDICATED_ROUTE

    Hello everyone, I use 1 pin of the pmod connector of the basys3 board for receiving a signal. So in the .xdc file i set every right but I need to say that the incoming signal is not a clock. In the help it suggests "set_property CLOCK_DEDICATED_ROUTE value [get_nets net_name]". I changed the net_name with the signal name "set_property CLOCK_DEDICATED_ROUTE value [get_nets echo_pin]" but u get this critical warning "Invalid option 'FALSEecho_pin' specified for'objects'. anyone an idee? thank you
  2. Hi, I am in the process of developing my own DDR2 controller as an exercise. Consequently, I'm trying to avoid using tools like MIG. Unfortunately I could not fully escape the clutches of automated tools, as in order to correctly configure the .xdc constraints file, I've had to have a peek at the following .prj file generated by the MIG in the official Digilent DDR2 Demo implementation: https://github.com/Digilent/Nexys-4-DDR-OOB/blob/master/src/ip/ddr/mig.prj I interpret the following line: "<InternalVref>1</InternalVref>" as setting the INTERNAL_VREF property to 1V. Therefore, I add the following line in my .xdc file: set_property INTERNAL_VREF 1 [get_iobanks 34] However, this configuration fails to implement for the Nexys4 DDR chip with the following error: [DRC 23-20] Rule violation (IVREF-2) INTERNAL_VREF - Bank 34 has INTERNAL_VREF set to an unsupported value (1.000V). Supported VREF values for this part are: 0.600, 0.675, 0.750, 0.900. Which value should I choose to use?
  3. Sam Bergami

    Vivado Constraints file .xdc

    Hi I am currently working on a project in Vivado 2017 using the external mux. I have more of a general question concerning the constraints file (.xdc). How does one go about creating their own xdc file? Normally, do you start with the full zedboard constraints file and comment things in yourself or can Vivado create one for you? Also is there a place I can look that explains the complete constraints file for the Zynq 7000 and when to use them? Thanks Sam
  4. db12321

    ARTY XDC Drive strength

    I am using an ARTY board. I have just used the constraints as is without making any changes. I do not see any constraints for drive strength or Slew rate attribute anywhere in the XDC file. I am wondering how it is determined that the default values are sufficient for these attributes. For example for the Ethernet PHY i browsed thru the datasheet but didnt see anything that would make it clear to select 12mA (default) drive strength for those pins.
  5. Hello It seems that Zybo Board files at Git are faulty. It gives some error messages, when connecting Leds to GPIO by assistant. See the picture. XDC master file has miss typo at one of VGA_R bits also.
  6. cbg

    "Cannot add Board Part" warnings

    Hi, I've been having this problem since I got the board and finally decided I want to get rid of it. I'm using a Nexys4 DDR Board and have downloaded the XDC file from the board website. In my projects I've got the board selected in my project settings as you can see. Nevertheless I always get these warnings which are really annoying. They are stating some completely different board and I've got no idea where they are coming from. Does anybody know how to get rid of them? By the way, at the Power tab at Project Summary window it always shows my confidence level as Low. I assume thats because most inputs are missing user specificatons as stated when you click on it. What setting sould I use for unused pins? At the moment the unused ones are simply commented out in the XDC file. Thanks!
  7. kgp

    Use Of On-board Clock In Basys3

    I got the following error when I tried the Generate Bitstream step. ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK. I am using the following statements in my .xdc file. set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK] What am I missing ? Please help!