Search the Community

Showing results for tags 'xdc'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Test and Measurement
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 13 results

  1. Hi All, I am working with a ZedBoard trying to test the output functionality of the Pmod headers. The Pmod headers on this ZedBoard have worked in the past, however, when I try to work with them now it appears that they do not transmit any output data. I've tried this for all four programmable logic accessible headers (JA1, JB1, JC1, JD1). When I assign the output to the LEDs I am able to see the output successfully, but it does not come through the Pmod headers. Here is a very simple HDL file and constraints file that I'm using on my ZedBoard that should produce output on the Pmod h
  2. rob2018t

    Arty Z7 and Reset

    Hello fellow Digilent Members, I hope everyone is well. My Skill Level: I'm slowly progressing my knowledge of FPGA and Vivado using the Digilent Arty Z7-20 and Arty S7-50. Essentially quite a beginner and I've created simple RTL designs to flash LEDs, utilised the Microblaze, Zynq and made a AXI-4 IP block. All really exciting stuff IMO...I just need to make something more useful now. My Question: when designing with the Arty S7-50 I'm able to specify the board and then drag across the reset into my top diagram and/or utilise that when auto completing the design. However in the
  3. I'm learning how to generate clocks with XDC files, using the .xdc from the Basys 3 github repository as a starting point. I'd like to change the clock to a very low frequency of 1 Hz, or once per second, so that a LED blinks on and off once a second. The portion of the .xdc file that generates the clock looks like this: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 1000000000.00 [get_ports clk] And the code for blinking the LED looks like this: module oneclock (
  4. hi everyone i want to test the example of soft error mitigation controller. I chacnge the constrains in the xdc file as below. # set_property LOC <pin loc> [get_ports monitor_rx] set_property PACKAGE_PIN L16 [get_ports clk] ##LED0 set_property PACKAGE_PIN M14 [get_ports status_initialization] ##LED1 set_property PACKAGE_PIN M15 [get_ports status_observation] ##LED2 set_property PACKAGE_PIN G14 [get_ports status_correction] ##JE1 set_property PACKAGE_PIN V12 [get_ports status_classification] ##LED3 set_property PACKAGE_PIN D18 [get_ports status_injection] ##JE
  5. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store
  6. Djsnzheusj

    ARTY A7-35 REV E.

    Hello guys, Im still starting off with FPGA's and i wonder if any one can point me to where the XDC file can be obtained for my board ARTY A7-35 REV E. the only master file i find is for the REV.D will it make a difference ? Thank you so much in advance.
  7. Hello everyone, I use 1 pin of the pmod connector of the basys3 board for receiving a signal. So in the .xdc file i set every right but I need to say that the incoming signal is not a clock. In the help it suggests "set_property CLOCK_DEDICATED_ROUTE value [get_nets net_name]". I changed the net_name with the signal name "set_property CLOCK_DEDICATED_ROUTE value [get_nets echo_pin]" but u get this critical warning "Invalid option 'FALSEecho_pin' specified for'objects'. anyone an idee? thank you
  8. Hi, I am in the process of developing my own DDR2 controller as an exercise. Consequently, I'm trying to avoid using tools like MIG. Unfortunately I could not fully escape the clutches of automated tools, as in order to correctly configure the .xdc constraints file, I've had to have a peek at the following .prj file generated by the MIG in the official Digilent DDR2 Demo implementation: https://github.com/Digilent/Nexys-4-DDR-OOB/blob/master/src/ip/ddr/mig.prj I interpret the following line: "<InternalVref>1</InternalVref>" as setting the INTERNAL_VREF property to 1V. The
  9. Hi I am currently working on a project in Vivado 2017 using the external mux. I have more of a general question concerning the constraints file (.xdc). How does one go about creating their own xdc file? Normally, do you start with the full zedboard constraints file and comment things in yourself or can Vivado create one for you? Also is there a place I can look that explains the complete constraints file for the Zynq 7000 and when to use them? Thanks Sam
  10. I am using an ARTY board. I have just used the constraints as is without making any changes. I do not see any constraints for drive strength or Slew rate attribute anywhere in the XDC file. I am wondering how it is determined that the default values are sufficient for these attributes. For example for the Ethernet PHY i browsed thru the datasheet but didnt see anything that would make it clear to select 12mA (default) drive strength for those pins.
  11. Hello It seems that Zybo Board files at Git are faulty. It gives some error messages, when connecting Leds to GPIO by assistant. See the picture. XDC master file has miss typo at one of VGA_R bits also.
  12. Hi, I've been having this problem since I got the board and finally decided I want to get rid of it. I'm using a Nexys4 DDR Board and have downloaded the XDC file from the board website. In my projects I've got the board selected in my project settings as you can see. Nevertheless I always get these warnings which are really annoying. They are stating some completely different board and I've got no idea where they are coming from. Does anybody know how to get rid of them? By the way, at the Power tab at Project Summary window it always shows my confidence level as Low. I assume thats because m
  13. I got the following error when I tried the Generate Bitstream step. ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports h