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Found 55 results

  1. Hi, I am using Xilinx XADC IP core for FFT operation and I have a couple of questions on the XADC sampling rate. Question 1) I would like to have the sampling rate at 1 MSPS but for a 100 MHz clock the XADC actual conversion rate is 961.54 KSPS. Same is for 50 MHz. I realized that for 104 MHz of DCLK clock the conversion rate is 1000 KSPS but implementing this clock from clocking wizard IP resulted in timing failure during implementation. (This is another problem if you have any inputs on how to tackle it) So I settled for 100 MHz clock and expected a 961.54 KSPS sampling rate. If I am not wrong the FFT resolution should be 961.54*10^3/4096 (for a 4096 point FFT). Backtracking from the scope, it appears that there is an offset from the expected sampling rate. Example: While 23.5 KHz is expected to fall in the 100th bin it falls in 111th bin. The sampling rate (computed from the FFT resolution formula - observing output) would be around 870 KSPS. Question 2) Would the sampling rate change if I use a 50 MHz DCLK clock instead of 100 MHz? The IP core indicates that the actual sampling rate would be 961.54 KSPS (same as that with 100 MHz clock) but I observed a shift in FFT output yet again. This time the sampling rate (computed from the FFT resolution formula) falls around 835 KSPS. Please help! P.S. - In my design I used a AXI-4 stream register slice as a pipeline stage to account for latency involved in multiplication and addition operations on the FFT output so that the signals from xfft_0 appear at the same time as the data. Frames are sent at the same rate (100MHz) at which the FFT is operated => BRAM read frequency = FFT CLK = 100 MHz. 3) Question on FFT: My FFT output appears to be almost as expected (except for the constant offset in frequency bins). After every 4095th bin there is a repetition of bin value 4080, (for a certain interval, until next 0) and I with a peak at this value. I do not understand the reason behind this. Please provide some insight on this as well.
  2. Hi there, I have been not having luck in reading the aux pins on the zybo z7 board. I have setup the system as below: The XADC is setup with DRP and channel sequencer in continuous mode, with the setup as below: I can read the voltages on the XADC system monitor dashboard as below: But the XADC only read 0x5999 on Aux 15 Pin, as seen below: As you will see above, Aux 6 and Aux 14 is stuck at 0x5999 and Aux 7 and Aux 15 is fixed at 0x5111. I don't get any errors only a critical warning: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. I have been debugging this for two days now and I am unable to fix this issue. So any help to get the analog inputs on aux pins converted is greatly appreciated! Cheers, Gautam.
  3. Hello, Merry Christmas hope you guys are doing great. I am a beginner in digital design course and i want to implement this xadc demo project from digilentinc reference on my Basys3 FPGA. I'm having problems on the step 4 which is running the project as i can't figure the physical connections to connect to the JAXDC port on FPGA. Can someone confirm if the connections i have done in this picture are right? One last question. When you open the XADC Basys3 Demo project and see its constraints, only package pins i don't understand are these A12,B13 ones. Where are they located on FPGA? I'm assuming there are some internal connections like seven segment decoder have. Any help appreciated. Thank You. Regards, Zain
  4. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? and also 3. How sensible are the XADC-Ports really? How high do currents and/or voltages have to be to cause damages? Are maybe the only important rules to prevent short circuits through XADC-hardware by placing a preresistor and prevent voltages above 3.3V? Thank you! /edit Question #4 Would a combination of resistors (one would be enough I think) and Zener-diodes (breakdown at 1V), as you can see below, securely protect any hardware onboard of any mistakes done outside XADC-Pmod? This is just a result of my tiny little knowledge of analog elecronics. Simulation does agree but that is just simulation. Maybe in reality and for a very short time there still could be constellations causing voltages and/or currents that could damage my board... Or is this schematic below really a secure protection? Depending on how XADC-hardware looks inside, theoretically a short circuit current would cause high voltages which should also be taken by the diodes, ...I guess. So are resistors maybe not even needed and only Zener-diodes would already give a safe protection of hardware damages?
  5. Hello, I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets". Design is below: As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. Pin assignment are as under for VC707 Schematics diagram for VC707 Any help will be appreciated. Thanks,
  6. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design ( with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  7. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect Pmod DA3 clock to XADC clock creating a unique clock for the entire design. This design was validated. Creating a HDL Wrapper, it has a correct synthesis, implemetation and bitstream. Programing the board i dont get any analog value for output Pmod DA3, it only works output LED[15:0]. Modules works correctly independently. Should i make a different connection for clocks? I dont know if there is a clock problem or other type problem. i attach the project Can anyone help me? Thanks! XADC + DA3.rar
  8. Kampi

    XADC - AD7 sampled on AD14

    Hello, I have a Zybo Board (Version 1 Rev. and I have a strange Issue with my XADC which samples the input for the channel AD7 on the channel AD14. Please take a look at my setup. I want to use the differential Channelpair 7 and 15 (like in the Photo - upper row VIn and lower row ground from my voltage source). My software gives me the results for channel 14 and 15 and the value for channel 7 stays constant even when I increase or decrease the input voltage. Only channel 14 and 15 change her values. I expect that channel 14 stays constant and channel 7 change his value. Temperature: 46.1576 Degree Celsius Vcc INT: 0.9961 V Vref+: 1.25 V Vref-: 3.00 V Channel 7: 2351 Channel 14: 26032 Channel 15: 32767 My code looks like this #include "stdio.h" #include "xparameters.h" #include "xadcps.h" XAdcPs XAdc; XAdcPs_Config* ConfigPtr; int main() { ConfigPtr = XAdcPs_LookupConfig(XPAR_XADC_DEVICE_ID); if(ConfigPtr == NULL) { xil_printf("Invalid XADC configuration!"); return XST_FAILURE; } XAdcPs_CfgInitialize(&XAdc, ConfigPtr, ConfigPtr->BaseAddress); if(XAdcPs_SelfTest(&XAdc) != XST_SUCCESS) { xil_printf("Self test failed!"); return XST_FAILURE; } XAdcPs_Reset(&XAdc); XAdcPs_SetSeqChEnables(&XAdc, XADCPS_SEQ_CH_AUX07 | XADCPS_SEQ_CH_AUX14 | XADCPS_SEQ_CH_AUX15); XAdcPs_SetSequencerMode(&XAdc, XADCPS_SEQ_MODE_CONTINPASS); xil_printf("Start...\n\r"); while(1) { u32 Temp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_TEMP); printf("Temperature: %.4f Degree Celsius\n\r", XAdcPs_RawToTemperature(Temp)); u32 VCCInt = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VCCINT); printf("Vcc INT: %.4f V\n\r", XAdcPs_RawToVoltage(VCCInt)); u32 VREFp = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFP); printf("Vref+: %.2f V\n\r", XAdcPs_RawToVoltage(VREFp)); u32 VREFn = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_VREFN); printf("Vref-: %.2f V\n\r", XAdcPs_RawToVoltage(VREFn)); u32 Ch7 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MIN + 7); xil_printf("Channel 7: %lu\n\r", Ch7); u32 Ch14 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX - 1); xil_printf("Channel 14: %lu\n\r", Ch14); u32 Ch15 = XAdcPs_GetAdcData(&XAdc, XADCPS_CH_AUX_MAX); xil_printf("Channel 15: %lu\n\r", Ch15); xil_printf("-------------\n\r"); for(u32 i = 0x00; i < 0xFFFFFF; i++); } return XST_SUCCESS; } With the following XDC file: ##Pmod Header JA (XADC) set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux14_v_p] set_property PACKAGE_PIN N16 [get_ports Vaux14_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux6_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux7_v_p] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_n] set_property IOSTANDARD LVCMOS33 [get_ports Vaux15_v_p] So what is going wrong here?
  9. Hello, I am using the Nexys A7-100T board.And I'm able to successfully read external input voltages on XADC Demo provided in the " ". I want to measure external input voltage(taken from measurement system) and show the parameter on PC. Now I try to modify the XADC Demo program,but I am still a beginner so I can't succeed. Please let me know how to do for making program. thanks marimo
  10. Hello, I am kind of new to FPGAs and I am trying to use the XADC in order to monitor the temperature sensor: I am using Vivado 2018.2, Nexys video as a board. I used the IP catalog in order to set up the XADC as following: DRP, Single channel, continuous, disable all alarms, disable reset_in, channel to monitor: temperature I wrote a top level module which reads the bits 4 up to 7 from do_out and light up LEDs accordingly: //part of the top module: module top( input CLK100MHZ, input vp_in, input vn_in, input [1:0] sw, output reg [11:0] LED ); wire enable; wire ready; wire [15:0] data; reg [6:0] Address_in; xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space .dclk_in(CLK100MHZ), .den_in(enable), .di_in(0), .dwe_in(0), .busy_out(), .vn_in(vn_in), .vp_in(vp_in), .alarm_out(), .do_out(data), .eoc_out(enable), .channel_out(), .drdy_out(ready)); always @( posedge(CLK100MHZ)) begin if(ready == 1'b1) begin case (data[7:4]) 4'b0001: LED <= 12'b000000000001; 4'b0: LED <= 12'b0; 4'b1000: LED<=12'b000000000010; default: LED <= 12'b1; endcase end end ///// I have one problem though, as I come to set the address of the ddr_in as done in a documentation found here which has LEDs displaying potential differences monitored by XADC, I do not understand what 8 bit address I should assign for the DRP to monitor the Temperature Channel ! "Address_in <= 8'h ????" My goal: I need the LEds to display something for the sake of demonstration that I am able to read values out of the do_out. Thank you for your help.
  11. Hi, Problem : I am new to FPGA and I would need to understand how to read an Analog input through the XADC to analyze it on the board and then be able to accordingly output a trigger for other machines. One simple thing that I would try to do for the time being is to read in the analog signal and wire it to a led so that I could effectively see the code is working. How do I do that ? Finally, one extra constraint is that I have to limit as much as possible the use of the Zynq processor (I'm not really sure this is achievable, please excuse my lack of knowledge). Product : I use the Zybo Z7 board XC7Z010-1CLG400C and Vivado Design Suite 18.3 What I have tried : I think the tutorial I've seen that best suits be needs is this one : Everything is alright until it comes to copy the instantiation template into the wrapper. I'm not really sure of how this works. After that, it is said there that the Digital input I'm interested in is named "daddr_in" ==> how should I extract it then to - let's say - connect it to a led ? Please find the Constraint file and project in the attached files and let me know if you need more. I have also made other attempts through this : Hence a question on the fly : when I open the SDK and enter a code in C, then I'm starting to ork on the PS isn't it ? Finally, I have also tried the XADC demo project on the digilent website but couldn't sort out how to adapt it to my needs. Thank you in advance for your healp, ! Zybo-Z7-Master.xdc design_1_wrapper.v xadc_wiz_0.v
  12. I'm attempting to use all 6 single ended ADC channels of the PYNQ-Z1 board with DRP enabled and with continuous sequencing (see attached configuration). According to the 7-series XADC guide UG480 on page 72, "When XADC is being operated in a sequence mode, you can identify the channel being converted by monitoring the channel address (CHANNEL[4:0]) logic outputs. The multiplexer channel address of the channel being converted is updated on these logic outputs when BUSY transitions Low at the end of the conversion phase." But the output of the channel (channel_out) is always zero, which I've worked around by outputting the previously selected channel with the data on the EOS signal. The issue is that it seems some of my samples are being labeled incorrectly, for example with a 500Hz signal on A4 and a constant 0.23V on A2 this is what I get: As you can see, it looks like some of the sinusoidal signal is being labeled as A2 and some of the DC is being labeled as A4. It would be much easier to debug what was going on if I could just read the channel_out signal with the conversion on EOS, but for whatever reason it always reads zero when I connect a wire to channel_out. Is there anything else I have to configure to get this to work correctly? Thanks, Chris xadc_wiz_0.v
  13. I am using zybo and block design flow to connect xadc ip to my system. But, the xadc is not giving out any info acquired from the outside. One forum mentioned that in case there is no instantiation xadc read internal voltage or temp. So I checked the wrapper and there is no instantiation of xadc. I am feeding the xadc with 100mhz clock. Should I change it? P. S; if I posted in the wrong forum please move my post. Thank you in advance for any help.
  14. Hello, I'm currently am trying to configure the XADC_wizard IP to receive audio from the mic_in port of the board. I have opened the XADC demo that was provided and saw in the Verilog code that the ports for the PMOD were instantiated. Leading to the ZYBO_Master.xdc I saw both the ##I2S Audio Codec and ## Audio Codec/external EEPROM IIC bus. Would either of these help me in setting up the mic_in port? Objective: receive external audio from the mic_in port, run it through the ADC, and view the data received and if possible view it in a waveform. Thank you
  15. Hello, I am using the latest version of XADC demo for Arty-Z7-10. In this demo, two switches should enable two XADC channels to be read from, however all of ADC channels (A0 to A11) are active together at the same time for different switch configurations which makes me think there is cross talk between these channels or XADC demo code is broken. Have anybody experienced this? I need to have three independent active ADC channels, while I have been able to use only one of them due to this cross talk issue. Best, Mahdi
  16. Hello! I have the following question. Is it possible to read Zynq temperature via XADC when working with Digilent Linux distro on PYNQ-Z1 board? Thanks!
  17. Hey, I want to use ZedBoard's XADC for sampling an external analog signal. Only one channel (single channel) is sufficient for now. Therefore, I tried to use the dedicated inputs, namely VP/VN in bipolar mode. When I check USERGUIDE480's page 32, the following picture is given: 1) From this figure, I understand that VN port must be supplied with an external 0.5 DC voltage source. Am I correct? Can i get this 0.5V dc from the ZedBoard not using an external supply source? 2) Is it enough I only connect VP/VN pins of XADC header leaving out other pins unconnected? I mean should I connect AGND or DGND to ground? thanks in advance, mehmet PS: Sorry, I posted this question to the incorrect sub-forum.
  18. When a custom bit files is used the petalinux fails. I am assuming the Petalinux build is expecting a PL XADC support? Is the a way to exclude this from the Petalinux build? Thanks Rick Linux version 4.9.0-xilinx-v2017.4 ([email protected]) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Thu Oct 11 15:36:08 EDT 2018 ........ usbcore: registered new interface driver usbhid usbhid: USB HID core driver Unhandled fault: imprecise external abort (0x406) at 0x000bc834 pgd = c0004000 [000bc834] *pgd=00000000 Internal error: Oops - BUG: 406 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-xilinx-v2017.4 #1 Hardware name: Xilinx Zynq Platform task: de44b640 task.stack: de44c000 PC is at xadc_axi_read_adc_reg+0x14/0x20 LR is at xadc_probe+0x430/0x6bc ....... [<c04e6eac>] (xadc_axi_read_adc_reg) from [<c04e8108>] (xadc_probe+0x430/0x6bc) [<c04e8108>] (xadc_probe) from [<c039dd38>] (platform_drv_probe+0x50/0x9c) [<c039dd38>] (platform_drv_probe) from [<c039c7d4>] (driver_probe_device+0x1b0/0x274) [<c039c7d4>] (driver_probe_device) from [<c039c914>] (__driver_attach+0x7c/0xa8) [<c039c914>] (__driver_attach) from [<c039b044>] (bus_for_each_dev+0x7c/0x8c) [<c039b044>] (bus_for_each_dev) from [<c039bf34>] (bus_add_driver+0x16c/0x1dc) [<c039bf34>] (bus_add_driver) from [<c039d030>] (driver_register+0xa0/0xe0) [<c039d030>] (driver_register) from [<c0101858>] (do_one_initcall+0x100/0x120) [<c0101858>] (do_one_initcall) from [<c0900da4>] (kernel_init_freeable+0x190/0x1d8) [<c0900da4>] (kernel_init_freeable) from [<c0603a98>] (kernel_init+0x8/0x10c) [<c0603a98>] (kernel_init) from [<c0106d18>] (ret_from_fork+0x14/0x3c)
  19. Is there a way to just input a voltage and read it through the terminal using the XADC Header on the Zynq 7000 Zedboard? If so can this be done using the VP VN pins?
  20. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  21. I am using XADC of Zybo board in DRP mode. I have connected the inputs of the XADC to a potentiometer supplying a voltage in between 0-1 V. I have used the PMOD pins to supply the output to external LEDs. But everytime the board is programmed, the LED outputs show a garbage value which is constant. Changing the potentiometer voltage does not change the outputs. Also resetting the XADC through GPIO buttons has no effect. Please help with the above issue.
  22. I have created a design in Vivado where I have used XADC with Zynq-7000 processor for acquiring a sine wave applied to the auxillary input of XADC. Now I have exported my hardware along with the bitstream file to the SDK. Now I want to create an application project in C/C++ for the corresponding design. I am facing problem in which header files to include and how to configure the code for proper implementation. Please help with the above issue.
  23. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  24. Hi, I tried the example project named Nexys Video XADC Demo present at the resource center. Before programming the FPGA, the voltage values of AD1, AD0, AD8, and AD9 are very low (20mV) w.r.t the ground. If the FPGA is programmed, the voltage of AD1, AD0, AD8, and AD9 jumps to 0.4V, even without any input to them (ADC pins are kept open). Besides, after programming, if i provide 500mv unipolar sine signal to just AD1, the sine signal is appearing at other pins such as AD0, AD8, and AD9. I am not able to understand the reason behind the voltage jump and why the signal given at one ADC appears at others before and after programming the FPGA. Help is much appreciated. Regards, Subash
  25. Hi, I am trying to implement xadc on my Zybo Board. I created the hardware and exported it to SDK. Then, I build an application for reading the on-chip sensor. But when I run the application, it stucks at XSysMon_CfgInitialize function. On debugging, I found that it is enabling DataAbortInterrupt. Does anyone have an idea abou this? Please find attached my hardware design, code, address editor tab screenshot and the tutorial that I followed to do it. Thanks & regards Vishav xadc_code.txt lab3.pdf