Search the Community

Showing results for tags 'xadc'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Calendars

  • Community Calendar

Found 30 results

  1. Arty XADC external voltage input

    Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the spec sheets but am still a beginner so I'm not always successful finding the right information. Greatly appreciate the help! Nystflame
  2. Channels in the XADC

    Hi all, again, I have a doubt and I hope I can help, I am working with the xadc of the nexys 4 DDR and I already manage to send the data of the xadc by uart to a graphic inetrfaz in matlab, the xadc owns 4 differential channels of entrance , when I want to see the data of one of the 4 channels I change the DADDR address (DADDR_IN [6: 0]), in the instanziacion of the xadc, which implies that it only allows me to see the data of only one channel at a time, my question is: is it possible to see two or more channels at the same time in real time? thanks
  3. UART and XADC

    Good morning, I am currently developing a graphical interface that allows visualizing the XADC data of the NEXYS 4 DDR, I found the problem that the UART communication protocol sends 8 bits as information, the xadc samples to 12 bits, someone knows some idea, solution or module that allows me to send the 12 bits of xadc by uart? Thank you
  4. Is there no other way?

    Greetings, I am trying to build a very simple digital signal processing circuit into my FPGA, Basys 3 board. Below you can find a simple block diagram. As you can see the components are, - A clock converter - An ADC ( embedded xadc) - A digital filtering operation H(e^jw) ( simple addition, multiplication circuit) - An SPI bus for communicating with an external DAC I have managed to build the clock converter, and the filtering operation. However, I have failed over and over again at building SPI and ADC blocks. Especially the XADC block gave me ( and still giving ) a hard time. I am aware that programming FPGAs can be very challenging. However, my question is... Is there no other way to do it? No simpler way to program my Basys 3 ? I have spent a good amount of time studying how to work with IP blocks, and the block diagram feature of Vivado. However, it does not work. Or I should at least say, it is not straight forward in any sense. It is not user friendly. My block diagram is really really simple. I connect all the necessary connections. Clock to clock, data out to.. etc. But I can't even get an analog reading on my Basys 3. Last but not least, there aren't any tutorials on working with XADC. The video about Basys 3 XADC, made by Xilinx, is a total joke. The other video, "teaching" how to use the IP generator for XADC is also another joke. These are 2-3 min videos, just showing you that IP generation feature does exist. They do not show how to use it in any way. This whole text is not a proper question, I am aware of that. Yet I am open to anything. Suggest me another, simpler way to code FPGAs. Suggest me another, more user friendly device. Suggest me an alternative platform to develop digital signal processing algorithms. Please. Sincerely, Berk
  5. XADC working without power supply?

    Hello guys. I was wondering how it is possible that the XADC in the Zedboard does actually convert data even though I didn't feed it with 1.8V power supply? I mean there is a physical pin but I'm not using it, so the XADC shouldn't work but it actually does. How come?Thanks.
  6. Zedboard Zynq 7000 XADC Header

    Is there a way to just input a voltage and read it through the terminal using the XADC Header on the Zynq 7000 Zedboard? If so can this be done using the VP VN pins?
  7. XADC PS side, zybo zynq

    Dear All, For the first time im trying to get the XMOD working with the PS side and print the values in a terminal. I tried a bunch of tutorials like the microzed chronicles.. I ended up using the tutorial posted as attachment, as attechments I also included my sourcecode and block design. I tried debugging by making several prints and I know the code works untll at least the "Test2" printf. During the build, no errors or anything appear. So i'm a bit confused into finding out where it all goed wrong. xadc.pdf design_1.pdf lab3.pdf
  8. How to constraint the XADC to external pins

    Hi, I am using XADC on Zybo board in PL.an external valtage in 0~1v is used. A simulation on the XADC is successful to be done,the results of transformation are correct. However, when I connect a external power to the pin, the result as showed on LEDs is wrong and the drdy is always zero .Is it the constraint wrong? My constraint is as follows. the pin2 as vauxp7 is connected to external power. the pin8 as vauxn0 is connected to GND. thanks for help! Sophia.
  9. Hi, I am using Vivado 2017.2. I cannot see the base system design when using the tcl script GPIO/xadc examples from the diligent website (follwing instruction as given here https://www.youtube.com/watch?v=eY8-qMB0ar0). It only gives me the option to create a new block design. Also, the among the GPIO/xadc examples only GPIO example works. Please, can you assist. Regards Sam
  10. Zybo XADC Demo

    Hello, I'm trying to run the file "XADC demo for ZYBO" with the tutorial "Using Digilent Github Demo Projects". First i downloaded the ZIP file "Zybo-XADC-2016.4-1" from "Github". I didn't select the “SDK Hardware Handoff” option because the project dose not supports Vivado SDK so i select the “Vivado” option. I did all the steps and when i get to step 3 "Generate Bitstream" ,I click Generate Bitstream on the left hand menu towards the bottom and click OK the "synthesis and implementation" are failed because 3 errors. i'm adding a print screen of the errors. Has anyone encountered this problem? Is there a problem with the file itself? Is there a problem with the C code? Thank you for any help!
  11. Getting weird values from XADC

    Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense. I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example. At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise. So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC? UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset?? Thanks in advance!
  12. (Not sure if this thread should go in Embedded Linux. If so, please feel free to move it) Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand. Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be: Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this: touch output ./streamread /dev/xillybus_datastream output This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000... Info: I generated the XADC using the wizard so I guess everything is properly instantiated. Tests I've run so far: I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well. Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was. This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high? I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it. Thank you (and sorry for the long post )
  13. XADC examples

    Hi, are there any XADC examples in VHDL? I found 4 examples which were in Verilog. I am currently trying to learn VHDL on the Arty-Board but couldn't find any helpful examples understanding the XADC. Any help is appreciated! Thank you!
  14. Hi, I am attempting to read a single-ended analog signal on one of ports A0 through A5 using the XADC in the Arty, but I am unable to connect the proper pins in a Vivado block diagram. Either the bitstream fails, or the C code never reads anything. I have a microblaze design that uses the AXI4 interface to the ADC, but still drives the temperature in the MIG and I followed one person's set-up of the XADC mentioned here, in order to still drive the temperature for the MIG7. I used this guide to do it: http://adiuvoengineering.com/?p=711 I have read everything I could on the matter in the Arty reference manual, but it doesn't mention how to tie these pins in Vivado in the block diagram: https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual Some things I have tried: I have enabled the Channel Sequencer in the XADC wizard and checked likely channels (like Vaux0, etc.). Doing a 'make external' on these new ports always fails implementation with issues related to improper IOSTANDARD on the bank of ports Manually hooking up the input pins by creating ports, hooking them to the XADC ports (like Vaux0), and using XDC constraints fail to implement with similar errors If I don't do 'make external' on any ports but the Vp_Vn one, then the bitstream generates, but the C code does not read any auxiliary channels. I have properly enabled all of them in the code and I loop through every channel to see what it registers. Temperature shows up just fine Is there a way to properly read the analog pins A0-A5 through the Vivado block diagram? Thanks!
  15. XADC on the Zybo

    OK, I've tried everything for a week. I simply cannot get any data out of my external sensors using the XADC. Can someone *please* give me some help. I'll attach my .v file, my .xdc file, and my IP file. You can ignore the LEDs being named in the constraints file. I was just playing around with them trying to get them to light up if I got any data come in the data in line. I had measured_aux0, measured_aux1, measured_aux2, and CHANNEL[4:0] in my module files, but it kept telling me there were not enough ports, so I took them out, and placed them as wires, etc. Maybe that is part of the problem? It even wanted me to place 'reset' in the .xdc file for some reason. Anyway, I'm worried that my .xdc file might be the problem. Thank you in advance for any help. xadc_wiz_0.xci top_design.v Zybo.xdc
  16. Hi, I have recently instantiated XADC in my block design in Vivado and connected Vaux14 as single channel, unipolar. I read voltages through IIO driver in Xilinx Linux. When I read internal voltages and temperatures, everything seems to be fine. However, when I try to measure voltage of battery (0.8 V) by connecting it to N15 and N16 (PMODs wired up with Vaux14 input), I get rather unsatisfactory results. Reading raw value and dividing it with 4096 I'm supposed to get real voltage, but I get stable value around 1300, which makes only around 0.3 after division. When I connect battery with lower voltage, I get lower value, but still not correct. Signal generator gives incorrect value as well. Am I missing something, what prevents me from getting expected results? Thanks for replies.
  17. Arty XADC power supply monitor

    Hello, I got an Arty board about two months ago and I'd like to use the power supply monitor feature. My main question is: "what's the appropriate sampling rate" Never used a 7 series FPGA before so I started reading through the XADC user guide [UG480] and the Driving the Xilinx Analog-to-Digital Converter [XAPP795] note. From what I understand (correct me if I'm wrong): Both inputs must be set to unipolar The XADC should be operated in simultaneous sampling mode to sample both voltage and current at the same time No auto-calibration in this mode. Calibration is done once at power-on The sampling rate should be low enough to cover the settling time of the analog input Looking at the respective circuit and assuming 12-bit accuracy, the settling time for the voltage sensing inputs [XAPP795,pp.2-8], [UG480,pp.79-80] is roughly tset = 9.01 * (8.33K + 8.25K + 1K + 1K) * 10nF ~= 1.67ms which implies sampling rates < 600 samples/sec if I don't want any gain errors. That's fine, but the problem is the XADC cannot be used for other, faster inputs we can't directly drive the XADC with the 100MHz board clock anymore, because the maximum ADCCLK divisor of 255 implies a minimum ~15Ksps/sec rate (not that big of an issue, plenty of PLLs in the chip - just worth mentioning) The few options I see are: Forget about mixing monitoring and higher rate signals in the same design Lower the bit accuracy and use averaging Live with the error at higher rates and use averaging Am I missing something here, do I have this whole thing completely wrong? Has anyone successfully used the monitor inputs in the Arty? (couldn't find anything online) Thanks, Lymperis
  18. XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  19. Hi: I was wondering if anyone has used the MicBlaze - AXI based access to the XADC to communicate with the AUX4 (XSM_CH_AUX4??) and AUX12 (XSM_CH_AUX12??) channels. Based on my read of the XADCdemo.sv and the comments, I guess the CMOD A7 analog inputs to be the XSM_CH_AUX 4 and 12 channels. I seem to be missing something with regards to how to initialize them. Thoughts? Peter
  20. Hi! I am trying to use the xadc demo project to read voltages from external sources. If I use a commercial power supply to supply a voltage, the system works well. The displayed voltage value is the same as that I measured using a multimeter. But if I use a transimpedance amplifier to convert a 1uA current to 122mV (confirmed by a multimeter) voltage as the input to the XADC, the displayed voltage value is incorrect. Actually, the voltage display is unstable, jumping among many weird values. I am wondering if there is a specific requirement for the input of the XADC? Hope someone can help! Thanks!
  21. XADC Simultaneous Sampling

    Hi,Even though I think this board should be towards questions about Digilent boards specifically, see if you can help me (I tried Xilinx forums without success). I am using the XADC's Vaux4 and Vaux12 on my Cmod A7. However, I'm having difficulties implementing the simultaneous sampling function using the XADC Wizard (Vivado 2016.2). From the wizard I get the ADC module with one address_in "pin" and one data_out "pin". My question is, if it is sampling both pairs simultaneously, how do I access the data? Wouldn't it be necessary to have two data outputs, one for each pair? How does it work? Thank you guys for your time and patience,Leo
  22. Analog read with Nexys4 DDR

    Hello! I have a Nexys 4 DDR. I'm trying to use an analog sensor like this: https://www.sparkfun.com/products/10264. I want to read data from it with a Nexys 4 DDR but I don't know how to do it. I have tried to read this document: http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf but I didn't understand how to do it. I use Vivado and VHDL. Can someone help me? Thank you!
  23. XADC output for module instantiation

    Hello all, I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter. `timescale 1ns/1ps module ug480_tb; reg [3:0] VAUXP, VAUXN; reg VP, VN; reg RESET; reg DCLK; wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX; wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX6, MEASURED_AUX7; wire [15:0] MEASURED_AUX14, MEASURED_AUX15; wire [7:0] ALM; wire OT; wire EOC; wire EOS; wire [4:0] CHANNEL; initial begin DCLK = 0; RESET = 0; end always #(10) DCLK= ~DCLK; // Instantiate the Unit Under Test (UUT) ug480 uut ( .VAUXP (VAUXP), .VAUXN (VAUXN), .RESET (RESET), .ALM (ALM), .DCLK (DCLK), .MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX6 (MEASURED_AUX6), .MEASURED_AUX7 (MEASURED_AUX7), .MEASURED_AUX14 (MEASURED_AUX14), .MEASURED_AUX15 (MEASURED_AUX15) ); integer i [0:4]; wire [15:0] e [0:3] reg [15:0] x [0:3]; initial begin for (i=0; i<4; i=i+1) begin x = MEASURED_AUX6; end end CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3])); endmodule Thank you, Shruthi Sampathkumar.
  24. Hello all, I'm trying to simulate LMS algorithm with digital samples from XADC out of Auxillary channel 6. In my step to update weight, I don't understand how to bring about weight update. It reads Weight_in and Weight_out as XXXX. Please check the bolded. area in LMS_weight module. *********************** module LMShruthi ( DCLK, RESET, Desired_in, mux ); input DCLK, RESET; input signed [15:0] Desired_in; output signed [15:0] mux; wire [15:0] mu; //mu=0.0000001 reg signed [15:0] Data_in; wire signed [15:0] e; wire signed [31:0] Product_32, y; assign mu = 16'b0000000001100110; always # (50000) Data_in = Desired_in; assign Product_32 = mu * Data_in; assign mux = Product_32[24:9]; LMS_weight uut3 ( .DCLK(DCLK), .RESET(RESET), .Data_in(Data_in), .mux(mux), .y(y) ); assign e = Desired_in - y[24:9]; endmodule *********************************************************** module LMS_weight (DCLK, RESET, Data_in, mux, y); input DCLK,RESET; input signed [15:0] Data_in,mux; output signed [31:0] y; wire signed [15:0] Weight_in; wire signed [15:0] Weight_out, emux; wire signed [31:0] Product_32; assign Product_32 = Data_in * mux; assign emux = Product_32[26:11]; assign Weight_in = (RESET==1'b1) ? 16'h0000 : (emux + Weight_out); assign y = Weight_out * Data_in; endmodule *********************************************************** Thank you, Shruthi Sampathkumar.
  25. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C). 1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values. 2. How many set of readings can I take? 3. Should the time be in millisecond, nanoseconds or seconds? Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained using Matlab 'audiorecorder'. data.xls