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Found 39 results

  1. mehmetdemirtas89

    ZedBoard XADC Header Dedicated Inputs

    Hey, I want to use ZedBoard's XADC for sampling an external analog signal. Only one channel (single channel) is sufficient for now. Therefore, I tried to use the dedicated inputs, namely VP/VN in bipolar mode. When I check USERGUIDE480's page 32, the following picture is given: 1) From this figure, I understand that VN port must be supplied with an external 0.5 DC voltage source. Am I correct? Can i get this 0.5V dc from the ZedBoard not using an external supply source? 2) Is it enough I only connect VP/VN pins of XADC header leaving out other pins unconnected? I mean should I connect AGND or DGND to ground? thanks in advance, mehmet PS: Sorry, I posted this question to the incorrect sub-forum.
  2. When a custom bit files is used the petalinux fails. I am assuming the Petalinux build is expecting a PL XADC support? Is the a way to exclude this from the Petalinux build? Thanks Rick Linux version 4.9.0-xilinx-v2017.4 (setup@usrd23715) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Thu Oct 11 15:36:08 EDT 2018 ........ usbcore: registered new interface driver usbhid usbhid: USB HID core driver Unhandled fault: imprecise external abort (0x406) at 0x000bc834 pgd = c0004000 [000bc834] *pgd=00000000 Internal error: Oops - BUG: 406 [#1] PREEMPT SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-xilinx-v2017.4 #1 Hardware name: Xilinx Zynq Platform task: de44b640 task.stack: de44c000 PC is at xadc_axi_read_adc_reg+0x14/0x20 LR is at xadc_probe+0x430/0x6bc ....... [<c04e6eac>] (xadc_axi_read_adc_reg) from [<c04e8108>] (xadc_probe+0x430/0x6bc) [<c04e8108>] (xadc_probe) from [<c039dd38>] (platform_drv_probe+0x50/0x9c) [<c039dd38>] (platform_drv_probe) from [<c039c7d4>] (driver_probe_device+0x1b0/0x274) [<c039c7d4>] (driver_probe_device) from [<c039c914>] (__driver_attach+0x7c/0xa8) [<c039c914>] (__driver_attach) from [<c039b044>] (bus_for_each_dev+0x7c/0x8c) [<c039b044>] (bus_for_each_dev) from [<c039bf34>] (bus_add_driver+0x16c/0x1dc) [<c039bf34>] (bus_add_driver) from [<c039d030>] (driver_register+0xa0/0xe0) [<c039d030>] (driver_register) from [<c0101858>] (do_one_initcall+0x100/0x120) [<c0101858>] (do_one_initcall) from [<c0900da4>] (kernel_init_freeable+0x190/0x1d8) [<c0900da4>] (kernel_init_freeable) from [<c0603a98>] (kernel_init+0x8/0x10c) [<c0603a98>] (kernel_init) from [<c0106d18>] (ret_from_fork+0x14/0x3c)
  3. Sam Bergami

    Zedboard Zynq 7000 XADC Header

    Is there a way to just input a voltage and read it through the terminal using the XADC Header on the Zynq 7000 Zedboard? If so can this be done using the VP VN pins?
  4. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================
  5. I am using XADC of Zybo board in DRP mode. I have connected the inputs of the XADC to a potentiometer supplying a voltage in between 0-1 V. I have used the PMOD pins to supply the output to external LEDs. But everytime the board is programmed, the LED outputs show a garbage value which is constant. Changing the potentiometer voltage does not change the outputs. Also resetting the XADC through GPIO buttons has no effect. Please help with the above issue.
  6. I have created a design in Vivado where I have used XADC with Zynq-7000 processor for acquiring a sine wave applied to the auxillary input of XADC. Now I have exported my hardware along with the bitstream file to the SDK. Now I want to create an application project in C/C++ for the corresponding design. I am facing problem in which header files to include and how to configure the code for proper implementation. Please help with the above issue.
  7. I am facing problem in how to use XADC wizard in Nexys 4 DDR board I just want to get the digital conversion of external inputs and access that 12bits of digital output directly. I am new to this and for now, I'm trying to just interlink XADC and a 12bits of DAC to convert an analog input(taken from a function generator) to digital(which will be stored in FPGA) and then use that digital data to generate the same signal at the output of a DAC. It will be really helpful If you can explain/provide a step by step process to do it. You can help using block design or a source code.... whichever way possible.
  8. Hi, I tried the example project named Nexys Video XADC Demo present at the resource center. Before programming the FPGA, the voltage values of AD1, AD0, AD8, and AD9 are very low (20mV) w.r.t the ground. If the FPGA is programmed, the voltage of AD1, AD0, AD8, and AD9 jumps to 0.4V, even without any input to them (ADC pins are kept open). Besides, after programming, if i provide 500mv unipolar sine signal to just AD1, the sine signal is appearing at other pins such as AD0, AD8, and AD9. I am not able to understand the reason behind the voltage jump and why the signal given at one ADC appears at others before and after programming the FPGA. Help is much appreciated. Regards, Subash
  9. Hi, I am trying to implement xadc on my Zybo Board. I created the hardware and exported it to SDK. Then, I build an application for reading the on-chip sensor. But when I run the application, it stucks at XSysMon_CfgInitialize function. On debugging, I found that it is enabling DataAbortInterrupt. Does anyone have an idea abou this? Please find attached my hardware design, code, address editor tab screenshot and the tutorial that I followed to do it. Thanks & regards Vishav xadc_code.txt lab3.pdf
  10. StudentAmsterdam

    XADC PS side, zybo zynq

    Dear All, For the first time im trying to get the XMOD working with the PS side and print the values in a terminal. I tried a bunch of tutorials like the microzed chronicles.. I ended up using the tutorial posted as attachment, as attechments I also included my sourcecode and block design. I tried debugging by making several prints and I know the code works untll at least the "Test2" printf. During the build, no errors or anything appear. So i'm a bit confused into finding out where it all goed wrong. xadc.pdf design_1.pdf lab3.pdf
  11. cristian_zanetti

    XADC conversion rate

    good day to all, my question is this: I am using the XADC of the Nexys 4 DDR, using the single channel mode, I want to sample at 1000 KSPS but using the IP CORE XADC Wizard it tells me that with these features the current conversion rate decreases to 961540 KSPS, I have searched the documentation of the XADC but I can not find a concrete answer to why this happens. If someone could help me, I would appreciate it.
  12. Hello, I was earlier able to flash LEDs on the Zybo 7010 board following the tutorials. However, I am currently trying to use the Zybo 7010 to flash LEDs which are external to the board. What I am looking at here is getting a constant voltage supply from one of the ports (maybe preferably the Xadc) to power the external LED circuit. I am having trouble getting a block design using the xadc_wiz_0 ip and the axi gpio with the zynq 7000 processor. Any information on this is greatly appreciated.
  13. I tried to build the XADC example project using , , and . Using Vivado 2016.4, after entering the tcl command "source ./create_project.tcl" I get ...# update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-2406] Cannot identify part xc7a200tsbg484-1 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' WARNING: [IP_Flow 19-2406] Cannot identify part xc7a15ticsg324-1L ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' (etc.) Using Vivado 2017.4, I get a lot farther. I clicked Generate Bitstream. While launching implementation run, I got a critical warning: [IP_Flow 19-4739] Writing uncustomized BOM file 'c:/Users/janko/Xilinx/Arty-Z7-20-xadc/src/ip/xadc_wiz_0/xadc_wiz_0.xml' The build subsequently failed. I found an answer (AR# 69645) on the Xilinx site related to the IP_Flow 19-4739 warning, but it wasn't helpful. There is indeed a file C:\Users\janko\Xilinx6\Arty-Z7-20-xadc\src\ip\xadc_wiz_0\xadc_wiz_0.xci (and nothing else) in that directory, but removing that file (as the AR suggests) doesn't help. How can I build this example project?
  14. Hi, I am attempting to read a single-ended analog signal on one of ports A0 through A5 using the XADC in the Arty, but I am unable to connect the proper pins in a Vivado block diagram. Either the bitstream fails, or the C code never reads anything. I have a microblaze design that uses the AXI4 interface to the ADC, but still drives the temperature in the MIG and I followed one person's set-up of the XADC mentioned here, in order to still drive the temperature for the MIG7. I used this guide to do it: I have read everything I could on the matter in the Arty reference manual, but it doesn't mention how to tie these pins in Vivado in the block diagram: Some things I have tried: I have enabled the Channel Sequencer in the XADC wizard and checked likely channels (like Vaux0, etc.). Doing a 'make external' on these new ports always fails implementation with issues related to improper IOSTANDARD on the bank of ports Manually hooking up the input pins by creating ports, hooking them to the XADC ports (like Vaux0), and using XDC constraints fail to implement with similar errors If I don't do 'make external' on any ports but the Vp_Vn one, then the bitstream generates, but the C code does not read any auxiliary channels. I have properly enabled all of them in the code and I loop through every channel to see what it registers. Temperature shows up just fine Is there a way to properly read the analog pins A0-A5 through the Vivado block diagram? Thanks!
  15. Nystflame

    Arty XADC external voltage input

    Hello, I am using the microblaze system with the xadc on an Arty board. I'm able to successfully read the internal voltages and temperatures of the chip, and I made some external pins (such as the VP/VN and Vauxp0 and Vauxn0). The pins which are external have been connected in a constraints file. My power supply positive terminal is hooked into the A0 port on my arty board, and the negative terminal is hooked into a gnd port. The XADC is attached to the AXI lite bus, controlled by the microblaze. Please let me know if any of this is unclear. P.S. I've looked into the spec sheets but am still a beginner so I'm not always successful finding the right information. Greatly appreciate the help! Nystflame
  16. cristian_zanetti

    Channels in the XADC

    Hi all, again, I have a doubt and I hope I can help, I am working with the xadc of the nexys 4 DDR and I already manage to send the data of the xadc by uart to a graphic inetrfaz in matlab, the xadc owns 4 differential channels of entrance , when I want to see the data of one of the 4 channels I change the DADDR address (DADDR_IN [6: 0]), in the instanziacion of the xadc, which implies that it only allows me to see the data of only one channel at a time, my question is: is it possible to see two or more channels at the same time in real time? thanks
  17. cristian_zanetti

    UART and XADC

    Good morning, I am currently developing a graphical interface that allows visualizing the XADC data of the NEXYS 4 DDR, I found the problem that the UART communication protocol sends 8 bits as information, the xadc samples to 12 bits, someone knows some idea, solution or module that allows me to send the 12 bits of xadc by uart? Thank you
  18. TheHowitzer

    Is there no other way?

    Greetings, I am trying to build a very simple digital signal processing circuit into my FPGA, Basys 3 board. Below you can find a simple block diagram. As you can see the components are, - A clock converter - An ADC ( embedded xadc) - A digital filtering operation H(e^jw) ( simple addition, multiplication circuit) - An SPI bus for communicating with an external DAC I have managed to build the clock converter, and the filtering operation. However, I have failed over and over again at building SPI and ADC blocks. Especially the XADC block gave me ( and still giving ) a hard time. I am aware that programming FPGAs can be very challenging. However, my question is... Is there no other way to do it? No simpler way to program my Basys 3 ? I have spent a good amount of time studying how to work with IP blocks, and the block diagram feature of Vivado. However, it does not work. Or I should at least say, it is not straight forward in any sense. It is not user friendly. My block diagram is really really simple. I connect all the necessary connections. Clock to clock, data out to.. etc. But I can't even get an analog reading on my Basys 3. Last but not least, there aren't any tutorials on working with XADC. The video about Basys 3 XADC, made by Xilinx, is a total joke. The other video, "teaching" how to use the IP generator for XADC is also another joke. These are 2-3 min videos, just showing you that IP generation feature does exist. They do not show how to use it in any way. This whole text is not a proper question, I am aware of that. Yet I am open to anything. Suggest me another, simpler way to code FPGAs. Suggest me another, more user friendly device. Suggest me an alternative platform to develop digital signal processing algorithms. Please. Sincerely, Berk
  19. gutielo

    XADC working without power supply?

    Hello guys. I was wondering how it is possible that the XADC in the Zedboard does actually convert data even though I didn't feed it with 1.8V power supply? I mean there is a physical pin but I'm not using it, so the XADC shouldn't work but it actually does. How come?Thanks.
  20. Sophia_123

    How to constraint the XADC to external pins

    Hi, I am using XADC on Zybo board in external valtage in 0~1v is used. A simulation on the XADC is successful to be done,the results of transformation are correct. However, when I connect a external power to the pin, the result as showed on LEDs is wrong and the drdy is always zero .Is it the constraint wrong? My constraint is as follows. the pin2 as vauxp7 is connected to external power. the pin8 as vauxn0 is connected to GND. thanks for help! Sophia.
  21. Hi, I am using Vivado 2017.2. I cannot see the base system design when using the tcl script GPIO/xadc examples from the diligent website (follwing instruction as given here It only gives me the option to create a new block design. Also, the among the GPIO/xadc examples only GPIO example works. Please, can you assist. Regards Sam
  22. eddya89

    Zybo XADC Demo

    Hello, I'm trying to run the file "XADC demo for ZYBO" with the tutorial "Using Digilent Github Demo Projects". First i downloaded the ZIP file "Zybo-XADC-2016.4-1" from "Github". I didn't select the “SDK Hardware Handoff” option because the project dose not supports Vivado SDK so i select the “Vivado” option. I did all the steps and when i get to step 3 "Generate Bitstream" ,I click Generate Bitstream on the left hand menu towards the bottom and click OK the "synthesis and implementation" are failed because 3 errors. i'm adding a print screen of the errors. Has anyone encountered this problem? Is there a problem with the file itself? Is there a problem with the C code? Thank you for any help!
  23. gutielo

    Getting weird values from XADC

    Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense. I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example. At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise. So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC? UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset?? Thanks in advance!
  24. (Not sure if this thread should go in Embedded Linux. If so, please feel free to move it) Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand. Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be: Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this: touch output ./streamread /dev/xillybus_datastream output This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000... Info: I generated the XADC using the wizard so I guess everything is properly instantiated. Tests I've run so far: I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well. Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was. This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high? I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it. Thank you (and sorry for the long post )
  25. MKVH28

    XADC examples

    Hi, are there any XADC examples in VHDL? I found 4 examples which were in Verilog. I am currently trying to learn VHDL on the Arty-Board but couldn't find any helpful examples understanding the XADC. Any help is appreciated! Thank you!