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Found 6 results

  1. When will the Microblaze Base System Design Tutorial be updated? I've tried following the one for the NEXYS4 board but the MIG for the DDR3 on the ARTY is not quite the same as the one for the NEXYS4. There is an extra reference clock on the MIG block and the the resets pins are routed to the processor reset block instead of the MIG reset block. Thanks
  2. Muthupriya Somasundaram posted this question on the Getting started with Vivado and Basys3 video: Hi, I registered in the digilentic forum, but i couldn't able to post any question. I am using a temperature sensor to measure the environment temperature and connected the sensor output to XADC. Now,form which pin do i need to get the binary output and the output will be in how many bits? Thanks in advance! Regards, Priya
  3. I am a teacher for Project Lead the Way and my course is Digital Electronics. In the course we use the CMOD S6 for about half of the course. Typically we use a program called Multisim to create circuits in what is know as PLD mode (Programmable Logic Device) and we export those programs via USB to the CMOD S6 that is attached to a specialty breadboard that can provide power, buttons, switches, etc. My issue is that I cannot find any documentation about what each of the 48 pins can be used for. We are told 24 and 25 are power and ground and we should use PIO14 to hook up an external clock but no reason is ever given as to why. Some of our logic programs only work if we use higher numbered pins and not lowered numbered ones. Some programs work with the onboard buttons, some programs can't use them. I am sitting in a class with 20 people trying to figure these nuances out and it all guess work. The product literature talks of multiple clock (signal voltage) outputs but not how to get them or how to change their frequency. Can anyone point me in the correct direction? Thanks, Tom Lum
  4. Here's a game of tic tac toe in VHDL for the Nexys4 DDR, written as a set of finite state machines and not as a computer running a program. The design is inspired from John F. Wakerly's tic tac toe code from his book "Digital Design: Principles and Practices", but I've completely rewritten it. The game logic is contained in the files TTTdefs.vhd, TwoInARow.vhd and game_logic.vhd. The rest of the code is there to interface with the user: to print strings to the user, to get digits and to control when moves are made. There are also two UART driver components. You should be able to set this up as a Vivado project by importing all the .vhd files and setting up the .xdc file as the constraints. When you run the bitstream, open up a 9600 bps serial connection to the Nexys4 DDR board and follow the instructions that you should see: Welcome to the computerless tic-tac-toe game. You get to make the first move. Please enter moves as digits from 1 to 9. What move would you like to make? Cheers, Warren (c) GPL3, 2015 tic_tac_toe.zip
  5. HI, I got my Nexys4 DDR about 3 weeks back, and I've been able to bring up my own microcoded CPU on the board. Lots of fun! I borrowed the UART transmit code from one of the examples in the Resource Center. Is there an example with UART receive code in it, or does anybody have a simple 9600,8,N,1 UART receive component which would work? Many thanks, Warren
  6. Hi everyone ! I need some help please : when I try to implement a counter in active HDL I have this warning message : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I explain : Firstly I have designed a basic counter with Basys2 board : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity counter_2 is generic (N : integer := 4); port( clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end counter_2; --}} End of automatically maintained section architecture counter_2 of counter_2 is signal count: STD_LOGIC_VECTOR(N-1 downto 0); begin process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end counter_2; Then I have produced 24-bit (q(23) downto q(0)) clock divider, my goal is to divide original frequency and obtain 2.98 Hz in using q(23) as output of the clock divider : library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity clkdiv2 is port( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end clkdiv2; --}} End of automatically maintained section architecture clkdiv2 of clkdiv2 is signal q: std_logic_vector(23 downto 0); begin process(clk, clr) begin if clr = '1' then q <= X"000000"; elsif clk 'event and clk = '1' then q <= q + 1; end if; end process; clk3 <= q(23); --clk48 <= q(19); --clk190 <= q(17); -- enter your statements here -- end clkdiv2; Finally I have used block diagram of the first counter and the clock divider to light the eight LEDs of Basys 2 as binary counter : ------------------------------------------------------------------------------- -- -- Title : count8_top -- Design : Counter -- Author : Unknown -- Company : Unknown -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\Example8\compile\count8_top.vhd -- Generated : Mon Jun 15 22:01:20 2015 -- From : c:\My_Designs\Example8\src\count8_top.bde -- By : Bde2Vhdl ver. 2.6 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; entity count8_top is port( clk : in STD_LOGIC; btn : in STD_LOGIC_VECTOR(3 to 3); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end count8_top; architecture count8_top of count8_top is ---- Component declarations ----- component clkdiv2 port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk3 : out STD_LOGIC ); end component; component counter_2 generic( N : INTEGER := 8 ); port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal clk3 : STD_LOGIC; begin ---- Component instantiations ---- U1 : clkdiv2 port map( clk => clk, clk3 => clk3, clr => btn(3) ); U2 : counter_2 port map( clk => clk3, clr => btn(3), q => ld( 7 downto 0 ) ); end count8_top; Finally when I implement the block diagram corresponding to the code above, I have this warning : " Route:455 - CLK Net:U1/q<23> may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template " I don't understand what does it mean. Could you help me please?