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I'm trying to put my own verilog module into official nexys video hdmi demo, but vivado 2016.4 keeps telling me "missing design sources" and reports error for implementation. I did as Xilinx says, declared a VHDL component then used named association to instantiate, is it better to declare an entity? EDIT: Verilog module(originally a testbench for another project): module testoverlay_0( input wire rst_n, input wire clk, output reg[23:0] RGBOut, output reg HSync1, output reg VSync1 ); VHDL: component testoverlay_0 is port ( rst_n: in STD_LOGIC; clk: in STD_LOGIC; RGBOut: out STD_LOGIC_VECTOR ( 23 downto 0 ); HSync1: out STD_LOGIC; VSync1: out STD_LOGIC ); end component testoverlay_0; test_overlay: component testoverlay_0 port map ( rst_n => reset_1, clk => sys_clk_i_1, RGBOut(23 downto 0) => v_axi4s_vid_out_0_vid_io_out_DATA_1(23 downto 0), HSync1 => v_axi4s_vid_out_0_vid_io_out_HSYNC_1, VSync1 => v_axi4s_vid_out_0_vid_io_out_VSYNC_1 );

Hi guys Sorry if I'm back i compiled the OOB design downloaded from your site, the ZIP file (dated 2 may 2017),,,,, the result is that Displayport continuates to be correctly trained and configured, but screen does not display. Additionally, in this version HDMI does not work too. At this point I suspect a problem in RTL (BD, constraints) sources. May you check the functionality of your distribution on a Genesys2 Board? Thanks in advance. P.S. Obviousy with other designs HDMI works fine, and with project available in flash displayport too,