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Found 182 results

  1. Hello, I want to use the AXI IIC bus Interface found in Vivado to read data from several MLX90393 sensors. My question is about the amount of AXI IIC interfaces needed for this. Is it enough to use only one, or is it necessary to use one for each sensor that will be used? Thanks in advance. MLX90393-Datasheet-Melexis.PDF
  2. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  3. Hi All, Is there anybody have any experience about XUP (Xilinx University Program) USB-JTAG Programmer Revision-G using with Vivado 2015 or 2018? I have some little experience with Vivado 2015.5 and 2018.1 but regarding my experiences XUP USB-JTAG Programmer is not compatible with Vivado? I tried all ways on Centos-7 OS and the particular script (install_drivers.tar.gz). I aimed to program the Zedboard for petalinux applications developing but no success with XUP USB-JTAG Rev.G and Vivado running on Centos-7. Could you please share any suggestions if you have? Regards. Kursat Gol
  4. I have created a design in Vivado where I have used XADC with Zynq-7000 processor for acquiring a sine wave applied to the auxillary input of XADC. Now I have exported my hardware along with the bitstream file to the SDK. Now I want to create an application project in C/C++ for the corresponding design. I am facing problem in which header files to include and how to configure the code for proper implementation. Please help with the above issue.
  5. Caleb

    Im completely new to this

    Hi, I'm just getting into programming FPGAs and I've made my first program "blinky light" but I cant get my computer to either find the FPGA when connected or I'm missing a step when I set up Vivado. I've ran the Synthesis, Implementation, and generated the bitstream and everything completed without any errors. I just need to know how to do last part which is to put the code on the FPGA. Thanks! What I'm using/running: Ubuntu 18.04 (OS on my computer), Vidado WebPack, Arty A7 35t, and if it helps I programmed it in Verilog
  6. mmmtgo

    unable to connect to hw_server

    this is my first attempt to program an FPGA (I use Basys 3), and when I tried to connect to the hw_server after generating the bitstream , I got this error:
  7. Abhinav Airan

    Pmod GPS not working

    I am using a pmod GPS with a zybo z7-10 board. However, even after running the sample code for the GPS, nothing is being printed on the serial monitor. I'm not entirely sure whether I have connected the pmod right, since there are 6 pins on the GPS but 12 pins on the pmod port. Nowhere has anyone mentioned whether one should connect the pmod GPS on the top six pins or the bottom six pins. Am I doing something wrong here or is there some other problem? I have also attached a picture of my block diagram for reference.
  8. smit

    Measuring time using a Zynq Processor

    I am working on the Zybo Z7-10 board. My goal is to determine the position and orientation of the FPGA in space at any given instance. For that, I am using a PmodACL2 and PmodGYRO. Now, I need to integrate the accelerations and angular velocities. How do I measure the time at which the Pmods are giving me the data?
  9. I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board. Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led? A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start! Here is myblock.v and part of my block diagram:
  10. fefernandezpy

    partial reconfiguration with nexys4

    Hi. I use nexys4 with vivado for do partial reconfiguration. After several test the open hardware manager lost comunication with nexys4. I can load simple .bit files and files of partial reconfiguration using PlanAhead, but I can not down again files using vivado. The same happened with 2 board nexys4. ¿What can I do?
  11. Nachiket Karve

    Connect two Pmods to the same port

    I recently started working on the zybo z7-10 board. I have two pmods - the PmodGPS and the PmodCON3. Both of these pmods have 6 pins each and I want to connect both of these pmods to the same port on the fpga. However, I could not connect the PmodGPIO_0 and the PmodGPS_0 blocks to the same port in my Block Design in Vivado. Is there any way to do this?
  12. I'm about to install Vivado on a new computer and want to know which version(s) will work for compiling the Arty Z7 and Arty A7 example projects. I'm asking because I've tried to use version 2017.4 twice and had problems each time, possibly due to version incompatibility problems. Using version 2016.4 resulted in success each time. In another thread, @jpeyron said "The xadc project was made for Vivado 2016.4. Unfortunately, the version does matter." Unfortunately, the "Installing Vivado and Digilent Board Files" document https://reference.digilentinc.com/vivado/installing-vivado/start (which is referenced at https://reference.digilentinc.com/reference/programmable-logic/arty/start?redirect=1, https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start, https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start, and probably lots of other project "start" pages) recommends using "Vivado Design Suite - HLx Editions - 2017.4 Full Product Installation"! So, does the 2017.4 HLx edition work with the Arty Z7 and A7 example projects? If not, the "Installing Vivado and Digilent Board Files" document contains bad advice, which can lead to users wasting hours or days of their time downloading and installing the software and then trying to get the projects to work. Please clarify which Vivado versions and Editions (plain Vivado vs. HLx) work with the example projects.
  13. Hello, I am currently following the first tutorial of the Zynq Book using the Zybo board and I am t the part where I am to launch the SDK after exporting hardware and receive the following error after the SDK loads up: 'Importing Hardware Specification' has encountered a problem. An internal error occurred during: "Importing Hardware Specification". java.lang.NullPointerException. Attached is a screenshot of the error. Thank you for any help.
  14. Hello,

    how to use the FMC (in zynq7000 zedboard) as A/D converter?

  15. I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created: I have a Video Test Pattern Generator connected to an Axi4-stream to Video Out IP driven by a Video Timing Controller IP. Here is a 100 ms simulation for the circuit: Vsync does not get generated, so clearly there is something wrong with this circuit. All examples I have found online include a MicroBlaze or Zynq processor with their design connected to the VTPG, could this be a reason my circuit is not working? Is it possible to do what I am trying to without a processor? What exactly is the role of a processor in these circuits? My development board is a Nexys 4 DDR. I've gotten VGA to display in the past using IPs I created myself, but they weren't AXI compliant. I have attached the tcl file to build my block design Any guidance would be appreciated! design_1.tcl
  16. tekson

    Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  17. deppenkaiser

    Arty-Z7-20 and Vivado 2017.4

    Hello, i was very happy, that i got the new 2017.4 Vivado design, but my happyness ends after five minutes. I have build Errors, can you please tell me what i have to do? Here is the screenshot: Thank you...
  18. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  19. davec

    Problems with MIG_7

    Has anyone had problems trying to use MIG_7 in their block diagrams in Vivado? I had a design that was working under version 2015.3, then something went wrong. Whenever I try to select that IP block in my diagram, vivado hangs trying to open it. I tried deleting it from my design and bring in a new mig_7series block from my list of board components and it hangs as well. I brought my design over onto a different Win7 computer and did a fresh install of a newer vivado 2017.3 with the latest board files with the exact same result- when I try to bring in the mig block, vivado hangs forever. Anyone know which files in my design I can remove to eliminate the bad references to the mig_7? tnx
  20. abcdef

    BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  21. Thausikan

    How to connect DMA with microblaze ?

    Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  22. samikhan0105

    Red Light Keep on glowing

    Hello Everyone, I am trying to accessing the Switch of my zybo and generating the string of character if the switch changes, everything is going fine and well compiled. But when i plug in my zybo there is a red LED that keeps on glowing I dont know what problem is this. THe Project is programmed in Zybo but its not running. Can anyone please help why its keep on glowing. Before some days it was not glowing. Regards, Sami
  23. It is my understanding that the dual processor in a ZYBO board can be used in parallel, each with their own code. I have a project where I need to run two parallel tasks, one of which was developed in SDK and the other in MATLAB using Embedded Coder. I know how to target a specific processor using Vivado/SDK, however, when using Embedded Coder in MATLAB this is more difficult to achieve and I haven't found a way to do it yet (i.e. I can upload my code onto the board but there's no indication of which processor it is using). Therefore, I was wondering if there is any way I can check the contents of the board using Vivado or SDK. Is there a way I can check which files the board is using and where these are being used? Alternatively, if anyone has any experience with MATLAB's Embedded Coder, could you let me know which generated files I could manually import into SDK to finish my application there? Many thanks.
  24. All, I'd like to continue an ongoing discussion that's now taken place across many forum threads, but I'd like to offer for everyone a simple place to put it that ... isn't off topic. (Thank you, @JColvin for inviting my ... rant) For reference, the tools I use include: Verilator: for simulating anything from individual components (such as this UART), to entire designs (such as my Arty design, CMod S6 design, XuLA2-LX25 design, or even my basic ZipCPU design). (Read about my debugging philosophy here, or how you can use Verilator here.) Drawbacks: Verilator is Verilog and System Verilog only, and things the Verilate don't always synthesize using Vivado. Pro's: compiling a project via Verilator, and finding synthesis errors, can be done in seconds, vice minutes with Vivado. Further, it's easy to integrate C++ hardware co-simulations into the result to the extent that I can simulate entire designs (QSPI flash, VGA displays, OLEDrgb displays, simulated UART's forwarded to TCP/IP ports, etc) using Verilator and (while it might be possible) I don't know how to do that with any other simulation tool. Time is money. Verilator is faster than Vivado. GTKWave: for viewing waveform (VCD) files yosys: Because 1) it's open source, and 2) it supports some (the iCE40 on my icoboard), though not all, of the hardware I own wbscope (or its companion, wbscopc): for any internal debugging I need to do. (Requires a UART to wishbone bus converter, or some other way to communicate with a wishbone bus within your design ...) Vivado: for synthesis, implementation, and any necessary JTAG programming wbprogram: to program bit files onto FPGA's. I use this after Vivado has placed an initial load onto my FPGA's. I also use wbicapetwo to switch between FPGA designs contained on my flash. zipload: to load programs (ELF files), and sometimes bit files, onto FPGA's ... that have an initial load on them already. While the program is designed to load ZipCPU ELF files, there's only two internal constants that restrict it to ZipCPU programs. ZipCPU, as an alternative to MicroBlaze (or even NiOS2, OpenRISC, picorv, etc). (GCC for compiling programs for the ZipCPU) The only program above that requires a license to use is Vivado, although some of the above are released under GPL Further, while I am solidly pro-open source, I am not religiously open source. I believe the issue is open for discussion and debate. Likewise, while my work has been very much Verilog focused, I have no criticisms for anyone using VHDL. To start off the discussion, please allow me to share that I just spent yesterday and today looking for a problem in my own code, given one of Vivado's cryptic error messages. Vivado told me I had two problems: a timing loop, and a multiply defined variable. The problem turned out to be a single problem, it's just that the wires/nets Vivado pointed me to weren't anywhere near where the error was. Indeed, I had resorted to "Voodoo hardware" (fix what isn't broken, just to see if anything changes) to see if I could find the bug. (Didn't find it, many hours wasted.) Googling sent me to Xilinx's forum. Xilinx's staff suggests that, in this case, you should find the wire on the schematic (the name it gave to the wire wasn't one I had given to any wires). My schematic, however, is .... complicated. Finding one wire out of thousands, or tens of thousands, when you don't know where to look can be frustrating, challenging, and ... not my first choice to finding the result. I then synthesized my design with yosys this morning and found the bug almost immediately. +1 for OpenSource. Time is money, I wish now I'd used yosys as soon as I knew I had a problem. Did I implement the design yosys synthesized? No. I returned to Vivado for ultimate synthesis, implementation, and timing identification.. If you take some time to look through OpenCores, or any other OpenSource FPGA component repository for that matter, you will quickly learn that the quality of an OpenSource component varies from one component to another. Even among my own designs, not all of them are well documented. Again, your quality might vary. +1 for proprietary toolchains, ... when they are well documented, and when they work as documented. There's also been more than one time where I've had a bug in my code, often because I've mis-understood the interface to the library component it is interacting with, and so I've needed to trace my logic through the library component to understand what's going on. This is not possible when using proprietary components--whether they be software libraries or hardware cores, because the vendor veils the component in an effort to increase his profit margin. Indeed, a great number of requests for help on this web site involve questions about how to make something work with a proprietary component (ex. MicroBlaze, or it's libraries) that the user has no insight into. +1 for OpenSource components, in spite of their uncertain quality, and the ability you get to find problems when using them. Another digital designer explained his view of proprietary CPUs this way, "Closed source soft CPUs are the worst of two worlds. You have to worry about resource use and timing without being able to analyze it". (Olof's twitter feed) In other words, when you find a bug in a proprietary component, you are stuck. You can't fix the bug. You can request support, but getting support may take a long time (often days to weeks), and it might take you just as long to switch to another vendor's component or work around the bug. +1 for OpenSource that allows you to fix things, -1/2 for OpenSource because fixing a *large* design may be ... more work than it's worth. Incidentally, this is also a problem with Xilinx's Memory Interface Generated (MIG) solutions. When I added a MIG component to my OpenArty design, I suddenly got lots of synthesis warnings, and it was impossible for me to tell if any were (or were not) valid. +1 for OpenSource components, whose designs allow you to inspect why you are getting synthesis warnings. I could rant some more, but I'd like to hear the thoughts others of you might have. For example, @Notarobot commented at the end of this post that, "using design tools introduces additional additional unnecessary risk. I'd like to invite him to clarify here, as well as inviting anyone else to participate in the discussion, Dan
  25. I need help in getting the Xilinx Vivado software to recognize the Digilent set of boards. Here are the steps that I have completed: (1) I successfully downloaded the webpack version of Vivado 17.4, and it is located at the following directory: C:\Users\David\AppData\Roaming\Xilinx\Vivado (2) I then successfully downloaded the Digilent support files for their new boards and unzipped it to the DS_Files directory as shown below: C:\Users\David\DS_Files\vivado-boards-master\new\board_files (3) I then opened the init.tcl file, as directed, and changed the first line as follows, so that when Vivado is launched, it will be directed to this file to include the Digilent boards when I select the board from within Vivado when starting a new project. As you can see, the <extracted path> is the same path as described in step (2) immediately above, so Vivado should know where to go to grab these new board files. set_param board.repoPaths load_features core enable_beta_device* (4) As directed, I then saved a copy of this new init.tcl file to the following two directory locations: C:\Users\David\DS_Files\vivado-boards-master\utility and C:\Users\David\AppData\Roaming\Xilinx\Vivado (5) According to the instructions, I was done with the necessary steps to download Vivado, modify the init.tcl file, and then place a copy of this new init.tcl in the above two directories. (6) I then restarted my computer, launched Vivado, and got to the point where I needed to select the board, however, Vivado did not display the list of Digilent Boards. Every time that I launched Vivado 17.4, it would not list the Digilent boards. (7) I then repeated steps (1) through (6) but with Vivado 16.4 and I still could not get Vivado to list the set of Digilent boards, even if I restarted my computer. I noticed that within the Vivado directory, a 2016.4 folder and a 2017.4 folder were created to separate both versions of Vivado, so within the Vivado directory, the inclusion of the init.tcl file as as follows: 2017.4 folder 2016.4 folder init.tcl (8) I have no trouble running either Vivado 17.4 or Vivado 16.4. I only have trouble getting either version of Vivado to recognize and list the set of Digilent boards when try to create a new project. Does anyone know why I can't see the list of Digilent boards when creating a new project? I am very frustrated at this point, hoping that someone in this forum can help me fix this problem. Thank you, ADN