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Found 203 results

  1. Hi Everyone, Just accidentally flashed the EEPROM attached to the FT2232 device on the Arty. The board is dead without the USB connection. Been using for 2 months without issues until today. In Vivado it is showing: "ERROR: [Labtoolstcl 44-469] There is no current hw_target.". when trying to Auto Connect with the target in Hardware Manager. Within FT_Prog (FTDI's flash tool), the registers (e.g. serial number, vendor ID, D2XX/VCP driver ...) can all be read and modified. How can it be restored back to Digilent factory setting? Is there an FT_Prog template that we can use? Thanks, Robin
  2. williams4564

    Basys3 Not recognized by Hardware manager

    When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  3. elizegi

    Change ZyBo Z7 FT2232 configuration

    Hi, I'm developing a design for the ZyBo and I'm using JTAG to communicate a PC with a microblaze. I'm using the onboard FT2232HQ to achieve this, but it is configured as UART -> Virtual COM Port and 245 FIFO -> D2XX Direct, so I can't see the JTAG connection as a COM port in the PC (which is what I need). I know that this can be changed using FT Prog, but I've seen that a lot of people had problems connecting the board with Vivado after changing the FT2232 configuration. Is it safe to make changes in the FT2232 configuration? Thanks, Xabier
  4. Hakob

    Vivado IP Interator SDK issue

    Hi All, I am beginner in FPGA world. I am trying to learn how to work with Vivado IP Integrator. When i try to launch my firstProj on Launch on Hardware(System Debugger) I am getting a such kind of issue: make all Building file: ../main.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"main.o" -I../../firstproj_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"main.d" -MT"main.o" -o "main.o" "../main.c" Finished building: ../main.c Building target: firstproj.elf Invoking: MicroBlaze gcc linker mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../firstproj_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "firstproj.elf" ./main.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: firstproj.elf section `.heap' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' makefile:35: recipe for target 'firstproj.elf' failed /opt/Xilinx/SDK/2018.2/gnu/microblaze/lin/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 1168 bytes collect2: error: ld returned 1 exit status make: *** [firstproj.elf] Error 1 19:49:21 Build Finished (took 335ms) I try to search on google but cannot to find an answer. Can someone help to understand the reason? I am thiinking that this may be some tool setup issue. Thanks!
  5. I seem to be having a similar issue with my Arty Z7 as this poster. At one point, my board was booting just fine from flash (via QSPI) or an SD card (with FSB, bistream, and SDK program). However, something happened along the way and I have to press the PROG button every time I power it up to boot it (true for either QSPI flash or SD). Only after I do this does the DONE light light up and the SDK program runs. My bitstream isn't compressed and I'm using Vivado 2018.2. I haven't messed with any of the bitstream or device properties. Any ideas? Thanks!
  6. I am a senior electrical engineering student and I just had my first interview at a local technology company and they offered me a second interview! However, they gave me a problem to solve of which i am pretty far into to it, at least far enough to start simulating some components. I am new to vivado and FPGA's in general and I have spent about 5 hours today trying to figure this error out. My code shows zero warnings or errors and I verified that the file in question is indeed in the directory that it is looking for. Wondering if anyone else has run into anything similar? Log Stuff: Tcl Console output when trying to simulate: launch_simulation INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-54] Inspecting design source files for 'Entry_MachineTB' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim' "xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj" The system cannot find the file specified. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds ERROR: [USF-XSim-62] 'compile' step failed with error(s) while executing 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. Batch File: 'F:/VHDL_Projects/Xilinx_Projects/Vivado_F5_CoffeeMaker/Vivado_F5_CoffeeMaker.sim/sim_1/behav/xsim/compile.bat' script is: @echo off REM **************************************************************************** REM Vivado (TM) v2018.3 (64-bit) REM REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM REM Generated by Vivado on Sat Jan 19 23:30:54 -0800 2019 REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 REM REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM REM usage: compile.bat REM REM **************************************************************************** echo "xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj" call xvhdl --incr --relax -prj Entry_MachineTB_vhdl.prj -log xvhdl.log call type xvhdl.log > compile.log if "%errorlevel%"=="1" goto END if "%errorlevel%"=="0" goto SUCCESS :END exit 1 :SUCCESS exit 0 I have verified that the "Entry_MachineTB_vhdl.prj" file is indeed in the same directory as the batch file. if needed, i can provide the code that i am working on. Thanks for any help provided!! :D
  7. Hi All, Is there anybody have any experience about XUP (Xilinx University Program) USB-JTAG Programmer Revision-G using with Vivado 2015 or 2018? I have some little experience with Vivado 2015.5 and 2018.1 but regarding my experiences XUP USB-JTAG Programmer is not compatible with Vivado? I tried all ways on Centos-7 OS and the particular script (install_drivers.tar.gz). I aimed to program the Zedboard for petalinux applications developing but no success with XUP USB-JTAG Rev.G and Vivado running on Centos-7. Could you please share any suggestions if you have? Regards. Kursat Gol
  8. josefoelias

    cora Z7 Vivado preset file for PS

    Hi there, Iam starting with your cora z7-10 board and I'm little confused with preset file mentioned few times on resource page. I am able to locate XDC master file but not preset file for PS. I am creating my own but I am not able to set voltage on MIO bank 501 to 1.0V as you have in description here on table 2.1 (second section) and I am missing signals like USB resetn... Can you point me to mentioned preset file for PS? Thanks a lot! have nice weekend! Joe
  9. That_Guy

    State machine vs Microblaze MCU

    So my current project is very simple, but I've yet to settle on how the control logic is going to be implemented. I think the FSM and Microblaze are both perfectly viable solutions, but I want to find the intersection of maximum learning and minimum complexity. The controller will be performing three tasks: -Pass alternating I and Q data from another module via usb to the user. -Receive data from the user via usb to set a desired frequency. -Interface with the clocking manager to request the new frequency. I am sure I could create an FSM to accomplish this, the USB controller has already been done, my hesitation is a lack of understanding of the AXI4 and DRP interfaces. I am familiar with 8-bit RISC AVR microcontroller, and if given a similar structure, I would think designing with a microcontroller would be almost trivial, but there is surely a learning curve to climb. The question boils down in my mind to a balance between the complexity of the FSM and the learning curve of Microblaze. I also am inclined to say some introductory experience with Mircroblaze would likely be desirable for a future employer. What do you think would be a better opportunity for learning?
  10. This issue had been a pain ever since I started using the CMDO-A7 devices. In Windows 7, using Vivado 2016.2, if I open the hardware manager in Vivado to configure the device, after a few minutes Vivado decides that the target is no longer available and disconnects it. This is a particular problem when I am also using the USB UART... though the problem doesn't happen immediately. This issue makes using the ILA extremely difficult to impossible with this board. When I use the Adept Utility for Windows to configure the board I can use the UART all day without a problem. I suspect a JTAG/UART driver related issue is to blame.
  11. All, I'd like to continue an ongoing discussion that's now taken place across many forum threads, but I'd like to offer for everyone a simple place to put it that ... isn't off topic. (Thank you, @JColvin for inviting my ... rant) For reference, the tools I use include: Verilator: for simulating anything from individual components (such as this UART), to entire designs (such as my Arty design, CMod S6 design, XuLA2-LX25 design, or even my basic ZipCPU design). (Read about my debugging philosophy here, or how you can use Verilator here.) Drawbacks: Verilator is Verilog and System Verilog only, and things the Verilate don't always synthesize using Vivado. Pro's: compiling a project via Verilator, and finding synthesis errors, can be done in seconds, vice minutes with Vivado. Further, it's easy to integrate C++ hardware co-simulations into the result to the extent that I can simulate entire designs (QSPI flash, VGA displays, OLEDrgb displays, simulated UART's forwarded to TCP/IP ports, etc) using Verilator and (while it might be possible) I don't know how to do that with any other simulation tool. Time is money. Verilator is faster than Vivado. GTKWave: for viewing waveform (VCD) files yosys: Because 1) it's open source, and 2) it supports some (the iCE40 on my icoboard), though not all, of the hardware I own wbscope (or its companion, wbscopc): for any internal debugging I need to do. (Requires a UART to wishbone bus converter, or some other way to communicate with a wishbone bus within your design ...) Vivado: for synthesis, implementation, and any necessary JTAG programming wbprogram: to program bit files onto FPGA's. I use this after Vivado has placed an initial load onto my FPGA's. I also use wbicapetwo to switch between FPGA designs contained on my flash. zipload: to load programs (ELF files), and sometimes bit files, onto FPGA's ... that have an initial load on them already. While the program is designed to load ZipCPU ELF files, there's only two internal constants that restrict it to ZipCPU programs. ZipCPU, as an alternative to MicroBlaze (or even NiOS2, OpenRISC, picorv, etc). (GCC for compiling programs for the ZipCPU) The only program above that requires a license to use is Vivado, although some of the above are released under GPL Further, while I am solidly pro-open source, I am not religiously open source. I believe the issue is open for discussion and debate. Likewise, while my work has been very much Verilog focused, I have no criticisms for anyone using VHDL. To start off the discussion, please allow me to share that I just spent yesterday and today looking for a problem in my own code, given one of Vivado's cryptic error messages. Vivado told me I had two problems: a timing loop, and a multiply defined variable. The problem turned out to be a single problem, it's just that the wires/nets Vivado pointed me to weren't anywhere near where the error was. Indeed, I had resorted to "Voodoo hardware" (fix what isn't broken, just to see if anything changes) to see if I could find the bug. (Didn't find it, many hours wasted.) Googling sent me to Xilinx's forum. Xilinx's staff suggests that, in this case, you should find the wire on the schematic (the name it gave to the wire wasn't one I had given to any wires). My schematic, however, is .... complicated. Finding one wire out of thousands, or tens of thousands, when you don't know where to look can be frustrating, challenging, and ... not my first choice to finding the result. I then synthesized my design with yosys this morning and found the bug almost immediately. +1 for OpenSource. Time is money, I wish now I'd used yosys as soon as I knew I had a problem. Did I implement the design yosys synthesized? No. I returned to Vivado for ultimate synthesis, implementation, and timing identification.. If you take some time to look through OpenCores, or any other OpenSource FPGA component repository for that matter, you will quickly learn that the quality of an OpenSource component varies from one component to another. Even among my own designs, not all of them are well documented. Again, your quality might vary. +1 for proprietary toolchains, ... when they are well documented, and when they work as documented. There's also been more than one time where I've had a bug in my code, often because I've mis-understood the interface to the library component it is interacting with, and so I've needed to trace my logic through the library component to understand what's going on. This is not possible when using proprietary components--whether they be software libraries or hardware cores, because the vendor veils the component in an effort to increase his profit margin. Indeed, a great number of requests for help on this web site involve questions about how to make something work with a proprietary component (ex. MicroBlaze, or it's libraries) that the user has no insight into. +1 for OpenSource components, in spite of their uncertain quality, and the ability you get to find problems when using them. Another digital designer explained his view of proprietary CPUs this way, "Closed source soft CPUs are the worst of two worlds. You have to worry about resource use and timing without being able to analyze it". (Olof's twitter feed) In other words, when you find a bug in a proprietary component, you are stuck. You can't fix the bug. You can request support, but getting support may take a long time (often days to weeks), and it might take you just as long to switch to another vendor's component or work around the bug. +1 for OpenSource that allows you to fix things, -1/2 for OpenSource because fixing a *large* design may be ... more work than it's worth. Incidentally, this is also a problem with Xilinx's Memory Interface Generated (MIG) solutions. When I added a MIG component to my OpenArty design, I suddenly got lots of synthesis warnings, and it was impossible for me to tell if any were (or were not) valid. +1 for OpenSource components, whose designs allow you to inspect why you are getting synthesis warnings. I could rant some more, but I'd like to hear the thoughts others of you might have. For example, @Notarobot commented at the end of this post that, "using design tools introduces additional additional unnecessary risk. I'd like to invite him to clarify here, as well as inviting anyone else to participate in the discussion, Dan
  12. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben
  13. dec

    Centos Vivado Xilinx JTAG Cable

    Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  14. Hello, I am new to ZYBO board. I am working on a project where I want to control a sensor from my ZYBO board using UART and receive the data from the sensor via SPI. I searched for the reference design, tutorials online to get started with, but I could not find any. Can anyone point me in the right direction where I can refer to and implement my work? THANK YOU. This is my aim as shown below. I want Zybo to be the main host, not my PC.
  15. yottabyte

    [Zybo Z7] Which Zynq to choose in Vivado

    please delete. thx /edit
  16. I've read the Reference Manual for ZyboZ7,it shows the Memory Part of ZyboZ7 is "MT41K256M16HA-125 DDR3L",but when I create a "helloworld" project in Vivado 2018.2,I did not see it at the list. So should I do something to add the suitable memory part in Vivado,or select someone to replace it? I've tried some memory parts,but they all failed,there was nothing displayed in the terminal.
  17. That_Guy

    Board repository path

    This seems like a silly question, but I've been told as a rule not to spend more than an hour on a silly problem. I am getting a healthy couple of warnings in Vivado about the board repository path (see attached). Just a typo, missed a backslash in the path. I've already made sure all Vivado_init.tcl files are correct. The project implements just fine, but I would love it if my warnings were meaningful, and I'd rather not suppress warnings How would I go about editing the path to resolve the warning? Cheers
  18. Weevil

    SPI-Flash CmodA7-35T Vivado 2017.3

    Hi all, i tryed to do the "How To Store Your SDK Project in SPI Flash" tutorial but i do not get it to work. Everything seems to be successful, but after rebooting the CmodA7 the .elf program i created does not start. During creating the project i followed the instruction from the attached post. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start) Additional i tryed to merge the .bit and .elf file with Vivado like the tutorial (https://techmuse.in/creating-and-configuring-xilinx-fpga-with-mcs/). Programming the fpga manual works, but if i try to write it in the flash the .elf program does not start. After programing the flash the bitstream is out of date (i don't know why). Maybe someone have an idea what i can do to get the merged bit file or mcs file on the spi-flash? Attached is my vivado project folder (http://www.mediafire.com/file/bq3ebw7b2dfpf72/Test_Microblaze.zip/file)
  19. Bui Cuong

    IP is locked and cannot be customized

    Hi everyone, My friend send me his project, but when I open it, it appear this error. All IPs is locked and cannot be customized. He and me use different vivado version. What is the problem ? The Pic: https://drive.google.com/open?id=1A0YhredaNk6Xr5VDGFh0XHj53PlmkfuX My project: https://drive.google.com/open?id=143_PRM7hTM-qg6JAXrBS_Tb-P-bnT5lR
  20. ATIF JAVED

    Implementation Problem in vivado 2017.4

    Hello all of you hope you are in a good health I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3] to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved Any kind of help in this regard is appreciable . Best, ATIF JAVED
  21. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  22. A recent change to the demonstration Cmod-A7-35 GPIO example (and others) here https://github.com/Digilent/Cmod-A7-35T-GPIO/commit/7bc1448626433ee2c2f493e48bf7b69a76b208b2#diff-a1605eb6dd43eccff08627ccfcfd10fd has removed the create_project.tcl file, which is referenced in your documentation here https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Can you please point me to updated "how to get started" documentation that is valid for vivado 2018.2 and the latest source code repository changes? Thank you
  23. abcdef

    BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  24. emarte

    Problem wih Arty S7-50 mapping I/o Pins

    Hello All! I have a Arty S7-50 Rev B Board. I am trying to control a mobile robot . I am also using a camera and to talk to both of them I need either I2c or serial communication. So far I created my system using microblaze with no problem. I tested leds, buttons, uart communication etc. My problem comes when I try to map pins other than buttons, leds or switch. I haven't been able to put the system to work. I Tried testing all I could think of before coming to the forums. I saved the project as another one, Created a new one from scratch etc etc and nothing so far. It have been many days if not weeks working in this part. I am pretty confidence about my design and about what I have to do with the robot. What I can't not is get signals out. So at this moment I'll give you some print screen of what I have. I could have some mistakes but it have been a lot of copy and paste and change so I got nowhere to go. I hope some of you could point me on where or how to go. I have this system with all this IP but at the beginning I was testing one by one. I need wither 2 uartlite o 1 I2c working. I know the microblaze, gpio0, timer and interrupt is working. Constraints: I had played a lot with this, this is the las I got. ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## Pmod Header JA #//set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { led2 }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] ## Pmod Header JD ##//set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33] set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { tx_1 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32] set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { rx_1 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31] set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { tx_0 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27] set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { rx_0 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26] set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { leds[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { leds[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { leds[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { leds[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit I2C set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Schematic Elaborated Design: From what I see eveything it is fine, isn't it ? I/O Pots on Schematic I/O Ports on Synthesized Design Code of Sliding LEDS using timer on LEDS: This is funny, these are some sliding leds. It does not matter where I put / map this pins on contraints, this always light the leds. I was tring to map this in pmod header JD but it just ligh the leds. Serial Test: Here the USB serial workf fine with the PC but the other 2 are sending nothing. I2C selftest. The selftest failed, I know it fails on XIic_SelfTest This board is brand new, I only have it for a few weeks. I havent connected anything to the ports. I measured pins either with a tester or with a analog discovery so not short ciruits or similar have been produced. Any help would be apreciated. Edwin
  25. Hello, I'm trying to configure my Basys 3 board to control a DC motor through the Pmod connector with an HB5 within Vivado. I've followed all steps in the Pmod IP tutorial but I'm stuck at 3.3. I'm not sure which specific pmod ip block I should use or how exactly to connect it. I couldn't find one corresponding to the hb5. Any advice would be greatly appreciated. Additional points: I don't need clocks or interrupts fed to the pmod I'm simply trying to control the operation (on/off) of the motor through one of the on-board switches. Thanks, gd