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Found 144 results

  1. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  2. Nexys Video No Hardware Target Exists

    I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  3. BASYS3 with Microblaze in Vivado 16.x

    I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2. I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works. However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below. My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2? Here is some additional information, for anyone interested: To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High. Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x: Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;) then File / Launch SDK. In SDK, use File / New Application Project and select the Hello World application. After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program. As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze. Strangely, the Microblaze design does not create any error messages or obvious warnings. Greatly appreciate any insight. Thanks.
  4. NEXYS4 board cannot be detected

    Hi, I just installed vivado 2017.2 on my PC, running windows 7 Service Pack1 (64-bit). I connected my Nexys 4 board using the cable that comes with the board in the package. When I attempted to connect the board to my PC, by clicking Open Hardware Manager -> Open Target -> Auto Connect, in the Hardware window in vivado, it shows localhost(0), which means no device detected. I also get 2 warnings below: warning: cannot open library dpcomm.dll, first required symbol ftdimgr_lock, Digilent FTDI based JTAG cables cannot be supported warning: cannot open library djtg.dll, first required symbol DjtgGetPortCount, select Digilent JTAG cables cannot be supported I noticed a post in a non-English Digilent forum, in which someone else was experiencing the exact same issue. Please help. yy
  5. Best Vivado license option on Zedboards

    Hello I want to buy a Zedboard to evaluate to possibly replacing our existing embedded computer solution (Kontron ETX computer module on a baseboard) with a ZYNQ 7000 based solution. I work at a research institute with a very strong mandate to train students. We will probably put a student on this job to investigate, so we might be able to qualify for the Academic edition of the Zedboard. My question is related to the licenses (vouchers) that come bundled with the zedboards by the various resellers. 1. On the site they state: A. (AES-Z7EV-7Z020-G) ZedBoard Commercial Edition (Available Exclusively from Avnet) I have contacted local Avnet rep which stated that this board comes with the Vivado HL Design edition node lock licence valid for 1 year. B. (ZEDBOARD) ZedBoard Academic Edition (Available Exclusively from Digilent) I have contacted digilent which indicate that this board comes with a node locked SDSoC licence valid for 1 year. 2. Looking at other suppliers like Digikey and Mouser ( you find -when searching the datasheet- that they provide a voucher for Chipscope licence only. You use webpack with these boards. Now I know that Vivado Webpack should be enough but I want to maximize value by purchasing the most valuable license for our particular application. I would want the student to have maximum flexibility. I think elements that are important are. 1. Good simulation and debugging capabilities i.e. embedded logic analyser, chipscope and a version of ISIM with more features than that shipped with webpack. 2. Good tools for C/C++ software development. We would be looking at integrating EPICS in our solutions. 3. Also access to more IP cores not available in Webpack would also be interesting to evaluate. We would be looking at integrating EtherCAT into our solutions. 4. It would also be nice to do High Level synthesis work (HLS) using C. Please advise me on which resellers' product supply the best/most valuable licensing option. Thank you Chris
  6. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!
  7. This issue had been a pain ever since I started using the CMDO-A7 devices. In Windows 7, using Vivado 2016.2, if I open the hardware manager in Vivado to configure the device, after a few minutes Vivado decides that the target is no longer available and disconnects it. This is a particular problem when I am also using the USB UART... though the problem doesn't happen immediately. This issue makes using the ILA extremely difficult to impossible with this board. When I use the Adept Utility for Windows to configure the board I can use the UART all day without a problem. I suspect a JTAG/UART driver related issue is to blame.
  8. Zybo webserver

    Dear, At the moment me and and a few friends are testing different IOT's. To upload data from a microcontroller or fpga to a webserver. Or upload to our website with $ comments. So our website will place the value's in the webserver. Now our question is. How can we connect our zybo board to the internet. We know we need to use the ethernet port but its very hard to find any information about uploading data with the zybo board. We use the zybo board with the vivado 2016 version. Greetings, Niels
  9. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  10. I'm attempting the GPIO demo with a new Arty Dev board and running into the following error. I'm following instructions here: Which is good until step #4. And if I uncheck "include bitstream", I get this error on the console: "Cannot write hardware definition file as there are no IPI block design hardware handoff files present" Since I'm new to Vivado development, this puts me at a dead stop. Thanks!
  11. Hi, I am running through the Creating a Custom IP core using the IP Integrator tutorial using Vivado 2017.2 and have run into a number of problems as follows. In section 4.1) Adding the the line, parameter integer PWM_COUNTER_MAX = 1024, Causes Vivado to mark the line with the warning, Warning: syntax error near "Integer". In section 4.2) Adding the lines, output wire PWM0, output wire PWM1, output wire PWM2, output wire PWM3, Causes Vivado to mark the first line with the warning, Warning: syntax error near "wire". In section 4.3) Adding the line, reg [15:0] counter = 0; Causes Vivado to mark the first line with the warning, Warning: syntax error near "15". Adding the remainder of this section causes a number of errors reporting that has not been declared. I have attached the VHDL file that I am working on. Any ideas why I am getting these issues? Forgive me as my VHDL is not very good at the moment and the issues I am having are probably only minor. Regards FarmerJo my_pwm_core_v1_0_S00_AXI.vhd
  12. Nexys4 DDR: Fix hold time violation

    Hi, I am using Vivado 2016.4 to program the Nexys4 DDR 7-segment display. I have a very simple VHDL project, which works as follows: 100 MHz clock is used to increment an 8-bit counter when this counter overflows, it inverts the value of a local signal called "slowclk". Hence, "slowclk" is "clk" divided by 512. the "slowclk" is used to increment another 8-bit counter, the output of which is assigned to the 7-segment display segment selector pins on the board. Complete VHDL source: Note: I understand that given such division, the effect on the digit segments will still not be visible - I just want to demonstrate the timing problem. However, the design fails to meet timing constraints as follows in attached pictures: Timing constraint failures in more detail, including the full source VHDL: Clock routing on the FPGA: The following is the .xdc constraints file (commented-out definitions are omitted): From what little I know about FPGA clock routing and resources, I understand this to be due to the high-frequency clock and associated logic being in different regions to each other, thus requiring the implementation run to route the clock signal through awkward paths; as a consequence, the total signal propagation time is such, that before the logic relevant to the current clock pulse is evaluated, the next clock front is already present. Am I correct in this thinking? And in either case, how can I fix the timing issues that Vivado warns about?
  13. Using Zybo Audio Codec W/base Design

    Hi all, I'm trying to get something working with the audio codec on the Zybo board. In the end, I want to sample an electronic musical instrument, do some signal processing, and output the processed signal, but for now I'm trying to get the demo from the base design working. I can get the demo to work using the supplied bit stream by creating an SDK project with the bitstream provided in the project files. If I open the PL project in a newer version of Vivado (2014.3), upgrade the IP cores, generate a bitstream, and run the demo from the SDK as before, the program hangs and doesn't print anything to the terminal. I've narrowed down where the program hangs using print statements to when the audio codec is being initialized. In particular, it seems that the code has an issue with the "Xil_Out32()" around line number 146 of the audio_demo.c file. To me this likely means that there is an issue with the programmable logic, so perhaps when I upgraded the IP cores for the new version of VIvado? I've also tried deleting the generic IP cores in the block design and running the connection automation, but with the same results. I am using an external supply to power the board with 5V and a max of 1A, so that shouldn't be an issue. I'm curious if anybody else has tackled something like this and/or updated the Zybo base design for newer versions of Vivado. -J
  14. How to add own logic to Arty board flow?

    The Arty board examples and tutorials use the Vidado drag and drop editor. But, there is no example how one would add their own custom logic. I have hacked this so far by dropping a peripheral and then replacing the stub verilog file, but it would help to show how this should be done. The natural would be to drop in a custom bus i/f file (e.g. using the AXI to AHB or AXI to APB bridge to a stub) and also how you add pins to the port list. Hacking away at it seems just wrong - if there is some intended flow, it is not apparent. The old way of editing the .ucf file and adding the ports to the top file does not seem like a fit for this SDK/Microblaze environment. Thanks, Paul
  15. Zybo XADC Demo

    Hello, I'm trying to run the file "XADC demo for ZYBO" with the tutorial "Using Digilent Github Demo Projects". First i downloaded the ZIP file "Zybo-XADC-2016.4-1" from "Github". I didn't select the “SDK Hardware Handoff” option because the project dose not supports Vivado SDK so i select the “Vivado” option. I did all the steps and when i get to step 3 "Generate Bitstream" ,I click Generate Bitstream on the left hand menu towards the bottom and click OK the "synthesis and implementation" are failed because 3 errors. i'm adding a print screen of the errors. Has anyone encountered this problem? Is there a problem with the file itself? Is there a problem with the C code? Thank you for any help!
  16. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  17. Centos Vivado Xilinx JTAG Cable

    Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  18. IP core with interrupts

    Hi, Can someone point to me please where can i find a tutorial/explanations how to use an IP core (in vivado) that interrupts the PS in a bare-metal application ? Until now i just created an IP for which I enabled "Interrupt suport"(created another interface for my block - S_AXI_INTR). By default, there is a timer(4 bits) which interrupts ARM in 10 steps. I followed this thread but is for microblaze and uses a axi interrupt controller. I want to link directly to PS because i have no other interrupts in the system. Regards, Mihai
  19. All, I'd like to continue an ongoing discussion that's now taken place across many forum threads, but I'd like to offer for everyone a simple place to put it that ... isn't off topic. (Thank you, @JColvin for inviting my ... rant) For reference, the tools I use include: Verilator: for simulating anything from individual components (such as this UART), to entire designs (such as my Arty design, CMod S6 design, XuLA2-LX25 design, or even my basic ZipCPU design). (Read about my debugging philosophy here, or how you can use Verilator here.) Drawbacks: Verilator is Verilog and System Verilog only, and things the Verilate don't always synthesize using Vivado. Pro's: compiling a project via Verilator, and finding synthesis errors, can be done in seconds, vice minutes with Vivado. Further, it's easy to integrate C++ hardware co-simulations into the result to the extent that I can simulate entire designs (QSPI flash, VGA displays, OLEDrgb displays, simulated UART's forwarded to TCP/IP ports, etc) using Verilator and (while it might be possible) I don't know how to do that with any other simulation tool. Time is money. Verilator is faster than Vivado. GTKWave: for viewing waveform (VCD) files yosys: Because 1) it's open source, and 2) it supports some (the iCE40 on my icoboard), though not all, of the hardware I own wbscope (or its companion, wbscopc): for any internal debugging I need to do. (Requires a UART to wishbone bus converter, or some other way to communicate with a wishbone bus within your design ...) Vivado: for synthesis, implementation, and any necessary JTAG programming wbprogram: to program bit files onto FPGA's. I use this after Vivado has placed an initial load onto my FPGA's. I also use wbicapetwo to switch between FPGA designs contained on my flash. zipload: to load programs (ELF files), and sometimes bit files, onto FPGA's ... that have an initial load on them already. While the program is designed to load ZipCPU ELF files, there's only two internal constants that restrict it to ZipCPU programs. ZipCPU, as an alternative to MicroBlaze (or even NiOS2, OpenRISC, picorv, etc). (GCC for compiling programs for the ZipCPU) The only program above that requires a license to use is Vivado, although some of the above are released under GPL Further, while I am solidly pro-open source, I am not religiously open source. I believe the issue is open for discussion and debate. Likewise, while my work has been very much Verilog focused, I have no criticisms for anyone using VHDL. To start off the discussion, please allow me to share that I just spent yesterday and today looking for a problem in my own code, given one of Vivado's cryptic error messages. Vivado told me I had two problems: a timing loop, and a multiply defined variable. The problem turned out to be a single problem, it's just that the wires/nets Vivado pointed me to weren't anywhere near where the error was. Indeed, I had resorted to "Voodoo hardware" (fix what isn't broken, just to see if anything changes) to see if I could find the bug. (Didn't find it, many hours wasted.) Googling sent me to Xilinx's forum. Xilinx's staff suggests that, in this case, you should find the wire on the schematic (the name it gave to the wire wasn't one I had given to any wires). My schematic, however, is .... complicated. Finding one wire out of thousands, or tens of thousands, when you don't know where to look can be frustrating, challenging, and ... not my first choice to finding the result. I then synthesized my design with yosys this morning and found the bug almost immediately. +1 for OpenSource. Time is money, I wish now I'd used yosys as soon as I knew I had a problem. Did I implement the design yosys synthesized? No. I returned to Vivado for ultimate synthesis, implementation, and timing identification.. If you take some time to look through OpenCores, or any other OpenSource FPGA component repository for that matter, you will quickly learn that the quality of an OpenSource component varies from one component to another. Even among my own designs, not all of them are well documented. Again, your quality might vary. +1 for proprietary toolchains, ... when they are well documented, and when they work as documented. There's also been more than one time where I've had a bug in my code, often because I've mis-understood the interface to the library component it is interacting with, and so I've needed to trace my logic through the library component to understand what's going on. This is not possible when using proprietary components--whether they be software libraries or hardware cores, because the vendor veils the component in an effort to increase his profit margin. Indeed, a great number of requests for help on this web site involve questions about how to make something work with a proprietary component (ex. MicroBlaze, or it's libraries) that the user has no insight into. +1 for OpenSource components, in spite of their uncertain quality, and the ability you get to find problems when using them. Another digital designer explained his view of proprietary CPUs this way, "Closed source soft CPUs are the worst of two worlds. You have to worry about resource use and timing without being able to analyze it". (Olof's twitter feed) In other words, when you find a bug in a proprietary component, you are stuck. You can't fix the bug. You can request support, but getting support may take a long time (often days to weeks), and it might take you just as long to switch to another vendor's component or work around the bug. +1 for OpenSource that allows you to fix things, -1/2 for OpenSource because fixing a *large* design may be ... more work than it's worth. Incidentally, this is also a problem with Xilinx's Memory Interface Generated (MIG) solutions. When I added a MIG component to my OpenArty design, I suddenly got lots of synthesis warnings, and it was impossible for me to tell if any were (or were not) valid. +1 for OpenSource components, whose designs allow you to inspect why you are getting synthesis warnings. I could rant some more, but I'd like to hear the thoughts others of you might have. For example, @Notarobot commented at the end of this post that, "using design tools introduces additional additional unnecessary risk. I'd like to invite him to clarify here, as well as inviting anyone else to participate in the discussion, Dan
  20. Hi I am using the Arty board by diligent. Can anyone please guide me to a tutorial to XADC Hardware build Thanks -Sam
  21. hello friends, how can i create a axi lite transaction to a axi full transaction , my slave transaction should be axi lite and my master transaction is axi full , i have created a peripheral in vivado in which my slave peripheral is axi lite and my master transaction is axi full, but when i port map, slave peripherals to master peripherals my addr bus of the slave peripheral is 4 bit and my master bus is of 32 bit bus. so im not able to port map it and create the exact transaction which i wanted kindly help ?? is there any other way?
  22. Vivado filter project

    Hello, I'm new in FPGA and I'm trying to realize a filter using the FPGA Nexys 4 on Simulink. I have already done the Simulink circuit and export it to the Vivado Design sout as a project. Here I choose the right FPGA but i have problem with I/O Ports planning. My output of this project will be a filter which will realize the filtration of biological signal (ECG) which i will bring on JXAD input port on FPGA. Can somebody please help me with realization in Vivado and tell me, which output can be the best after the filtration? Your help means very much to me...
  23. Hi, I want to implement in Vivado a hardware implementation which will program the FPGA to create 4 register of 128 bit data and 4 comparators. First entries of the comparators will be linked to these 4 registers and the other entries will be linked to a single 128 bit register received from PS. I attached i picture (A picture is worth a thousand words). Please guide me with an exemple, start point in solving this issue.
  24. Program CMod A7 35T without Vivado

    Hi, I have a question, there is a way to programm my Cmod A7 without Vivado->Hardware Manager? I got some issues with Vivado, sometime crash. Another question is, there is a way to separate programming phases? At moment i have a download.bit, firmware.srec and data.txt, with hardware manager i have fused them in firmware.mcs and have flashed it in my SPI Flash. There is a way to program my flash only with download.bit and firmware.srec and later with data without overriding the other memory banks? Kind Regards Stefano
  25. Hi, I am attempting to read a single-ended analog signal on one of ports A0 through A5 using the XADC in the Arty, but I am unable to connect the proper pins in a Vivado block diagram. Either the bitstream fails, or the C code never reads anything. I have a microblaze design that uses the AXI4 interface to the ADC, but still drives the temperature in the MIG and I followed one person's set-up of the XADC mentioned here, in order to still drive the temperature for the MIG7. I used this guide to do it: I have read everything I could on the matter in the Arty reference manual, but it doesn't mention how to tie these pins in Vivado in the block diagram: Some things I have tried: I have enabled the Channel Sequencer in the XADC wizard and checked likely channels (like Vaux0, etc.). Doing a 'make external' on these new ports always fails implementation with issues related to improper IOSTANDARD on the bank of ports Manually hooking up the input pins by creating ports, hooking them to the XADC ports (like Vaux0), and using XDC constraints fail to implement with similar errors If I don't do 'make external' on any ports but the Vp_Vn one, then the bitstream generates, but the C code does not read any auxiliary channels. I have properly enabled all of them in the code and I loop through every channel to see what it registers. Temperature shows up just fine Is there a way to properly read the analog pins A0-A5 through the Vivado block diagram? Thanks!