Search the Community

Showing results for tags 'vivado'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Calendars

  • Community Calendar

Found 163 results

  1. Hello, I have written many VHDL configurations, however, I am now working with block designs on VIVADO and am having trouble figuring out how to interconnect a binary counter with outputs Q[8:0] to inputs discrete logic ANDs ORs NOTs of various [?:?]. I need to do this so that I can determine multiple output values of the 9bit count. I would also need to know how to do this for other discrete logic circuits. Also any information about using wrappers to import the design into a VHDL usage would be helpful as that would be the next step. The specific trouble seems to be that when I connect Q[8:0] to OP[3:0] it just draws a bus and doesn't specify which actual pin configuration is present nor how to select which it should be. I have also gone thru several Xilinx reference materials on VIVADO and none of the techniques I have found demonstrate nor explain how to do this specific task. Thank you in advance Sincerely DC PS. 2 more considerations after I created this post 1) placing this circuit into a stand alone block IP circuit 2) Interconnecting directly TO FPGA IOs
  2. Hi, I am relatively new to FPGA programming and purchased recently the Zedboard. I am trying to implement a simple blinky Verilog design, written in Vivado, on the Zedboard. The Zedboard is connected via two ordinary USB cables to the Laptop - one from J17, one from J14. I am able to log into the Linux part of the Zynq and do all demos, but have no success implementing the blinky design into the FPGA part due to the "Program Device" option in Vivado staying grayed out after generating successfully the bitstream and trying to connect to the device. There seems to be an issue with the connection to the board (I am getting the message board not connected or not powered). The last step to "Program Device" is never available. I tried about 10 installations with different Vivado WebPack revisions and on 3 different laptops (2 with Windows 10, one with Windows 7). I tried also updating cable drivers and modifying the jumpers JP7 to 11 to different configurations. "Program Device" stays grayed out. I am out of ideas and am hoping someone can give me a hint what is going wrong. Thanks
  3. Memory tutorial

    Hi I am beginning my foray into FPGA design, and I decided that the best to to learn would be to learn on the go, and learn as I go. I am using a Zybo Z7 7020, Windows 10, and Vivado 16.4 I have a project for school which will be using PMODs as IOs and the information will have to be saved to memory of the board I am wondering if there is a good tutorial which will help me learn how to access, read and write to the DDR3
  4. Which version of Vivado should I use

    Hi! I am new to this and I have a project for school so this will be the first of many questions I have a Zybo Z7 7020 and I am running Windows 10 For now, I plan on using the free version of Vivado. My project will involve using the PMOD as IO and using the HDMI output. I understand that in order to program the Zybo, I need the board files and the library files in order to use the IPs In order to have the best compatibility, which version of Vivado should I use? Does it matter? Why?
  5. I need a few units of a development kit, the less expensive, which can provide partial and full dynamic reconfiguration. Also, I would like to know if such board works with microblaze. Can anybody indicate a good product? From Digilent?
  6. Vivado not finding Arty target

    I've installed Vivado v2017.4 on a CentOS 7.4 system. The ARTY board JTAG/UART is connected to a USB port on the host system. When I start Vivado, and start the Hardware Manager, it shows that there is a server running on "localhost" but does not list any target boards. Clicking on "Auto Connect" does nothing. The Hardware Server Properties window says that Vivado is connected to the server. Running "lsusb" on the host shows two ftdi_sio USB Serial Devices which are attached to /dev/ttyUSB0 and /dev/ttyUSB1. Any suggestions?
  7. FPGA Initialization failed

    getting a error while i am trying to program FPGA (zybo) with Pmod:ACL in Xilinx sdk.
  8. [Help/Advice] Read address from DDR and print it

    Hi, i would like to just be able to read memory addresses from RAM on my Zybo Zynq -7000. I have read some interesting articles including this one http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html I followed every step but I'm still missing the part where i can e.g. just read an address print it out (and write it back?). If this could be done with the SDK in c/c++ it'd be awesome . Could anyone recommend me some literature or is there a tutorial which i can follow to understand this better ? Thanks in advance
  9. Zybo placing error

    i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period ); the log file is attached , thank you implem_log.txt
  10. How to connect DMA with microblaze ?

    Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  11. I have an Arty-35 evaluation board that came with a device-locked, node-locked Vivado license. (BTW, the board and tools are very nice). Does my limited Vivado license also cover programming the Cmod A7: Breadboardable Artix-7 FPGA Module which also uses an Artix-7 A7-35T FPGA component? I think they're the same Artix-7 device, so it seems like it should work. I'd like to purchase one of these Cmod A7 FPGA DIP devices, but I want to be sure my Vivado license will cover it.
  12. arty xc7S50 vivado support win 8.1

    which version of the vivado do I need for win 8.1 xc7S50 arty board thanks in advance DC note 2014.4 doesn't have the chip listed note 2017.4 says its for windows on the install page but then later says it don't support 8.1 and also crashes on 8.1
  13. Hello, I am following this tutorial for microblaze for the nexys 4 ddr: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start?redirect=1 I am getting an error for the mig_7_series... generation that is outlined when I try to generate the bitstream in step 14. It looks like it is pulling the mig from Xilinx's core generation, is it supposed to be using the mig from the nexys 4 ddr files instead? Here is my error output: Another thing to note, I have a space in the directory path, is that the issue possibly? It is not complaining about anything else though. I have also verified that the file it "can't find" is actually there and has contents. I'm running Vivado 2017.4 WebPack, but I can't imagine this would cause issues for a Xilinx IP core, maybe for IP cores from Digilent. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_uartlite_0 . error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2017.4/data/ip/xilinx/mig_7series_v4_0/xit/synthesis.xit': error deleting "C:/Users/Glen Nicholls/Desktop/fpga_dev/boards/nexys_4_ddr/proj/microblaze/microblaze_intro.srcs/sources_1/bd/microblaze_intro/ip/microblaze_intro_mig_7series_0_0/microblaze_intro_mig_7series_0_0\example_design\rtl\traffic_gen\mig_7series_v4_0_cmd_prbs_gen_axi.v": no such file or directory ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s). ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'mig_7series_0'. Failed to generate 'Synthesis' outputs: ERROR: [BD 41-1030] Generation failed for the IP Integrator block mig_7series_0 INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_mig_7series_0_81M .
  14. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board. The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design). However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design). Can anyone help me figure out why this is happening? Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board: SOURCES: ---------------- -- pindelivery.vhd -- Routes package pins to logical units library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity pindelivery is Port ( clk_in : in STD_LOGIC; rst_in : in STD_LOGIC; leds_out : out STD_LOGIC_VECTOR (3 downto 0)); end pindelivery; architecture behavioral of pindelivery is component topLevel_debug port (clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector(3 downto 0)); end component; signal rst_out : std_logic := '0'; begin rst_out <= not rst_in; tld1 : topLevel_debug port map (clk => clk_in, rst => rst_out, led_out => leds_out); end behavioral; ---------------- -- topLevel_debug.vhd -- Top-level module for debug library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity topLevel_debug is port ( clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector (3 downto 0)); end topLevel_debug; architecture behavioral of topLevel_debug is component controlTest port (clk : in std_logic; rst : in std_logic; r0_highnibble : out std_logic_vector(3 downto 0)); end component; begin cpu1 : controlTest port map (clk => clk, rst => rst, r0_highnibble => led_out); end behavioral; ---------------- CONSTRAINTS: ---------------- ## Clock signal set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }]; ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Reset button set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property INTERNAL_VREF 0.675 [get_iobanks 34] ---------------- Any assistance would be much appreciated! Thanks, Curt Pehrson
  15. PMODGPIO build on Zybo (2016.4)

    I am attempting to build upon the hdmi demo, here is what I want to accomplish: Take over PMOD_C port as a general purpose digital output (8 pins) Here is what I have done (aside from debugging for hours) I dropped down and wired a PmodGPIO_0 block in my design and connected it to PMOD_C (JC), used the auto-connection automation function in Vivado. The build seems to work just fine, exported hardware, etc as normal. In SDK I get a drivers/ directory in hw_patform_1 with PmodGPIO_v1_0 and everything looks fine. Here are the exact steps I followed from here to where I am now: copied PmodGPIO.h down to hdmi/src (build project directory) copied code (functions) from PmodGPIO.c into video_demo.c (build main .c) copied code (init, main, close) from output_demo.c into appropriate places in video_demo.c Question 1) The code would not execute, because it appears the XPAR_ for PMODGPIO does not feed correctly into xparameters.h. Is this normal? I tried to workaround by checking system.hdf and found the base address for my PMODGPIO 0x40000000 and hard-coded it. This would allow the code to compile, but it does not run correctly, it hangs in GPIO_begin on the statement Xil_Out32(InstancePtr->GPIO_addr+4, bitmap);. This is the first statement where it attempts to write to the mapped memory. I have a feeling that something with the PmodGPIO IP is not building correctly for me, but I don't know how to correct it. I have tried several times to clean and rebuild the project, but again I don't know if I am taking the right steps. Question 2) Is there some type of 'build' that I need to do in SDK or somewhere else to initialize the IP correctly and be able to write to the PmodGPIO ? Thanks!
  16. Vivado HLS

    Hi, Do you have any experience of using Vivado High Level Synthesis, HLS? Today I use VHDL and C/C++ in microblaze. I am interested in testing HLS but don't know if it is worth spending time on that. Is it easy to get things running using HLS? What are the main pro/cons using HLS instead of VHDL/Verilog? Are the tools mature? Best regards
  17. Vivado CLOCK_DEDICATED_ROUTE

    Hello everyone, I use 1 pin of the pmod connector of the basys3 board for receiving a signal. So in the .xdc file i set every right but I need to say that the incoming signal is not a clock. In the help it suggests "set_property CLOCK_DEDICATED_ROUTE value [get_nets net_name]". I changed the net_name with the signal name "set_property CLOCK_DEDICATED_ROUTE value [get_nets echo_pin]" but u get this critical warning "Invalid option 'FALSEecho_pin' specified for'objects'. anyone an idee? thank you
  18. Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...
  19. are there any tutorials for dummies on getting a zybo board to produce a tone? one that thoroughly explains its steps?
  20. Hello, I have a Nexys 4 DDR board and I was going through the tutorial. I installed the suite and when I reach the point to connect the target, Vivado is unable to find it. The jumper of the JTAG is right and I tried more than one USB cable. The error I get on Vivado is "No hardware targets exist on the server [TCP:localhost:3121]" Your help is appreciated. Ahmed
  21. Greetings, I am currently working on a Digilent Zybo Trainer Board with a Zynq 7010 chip. Everything works fine from hardware up to software running on the board as long as it is launched directly from the Xilinx SDK. However, the software hangs up indefinitely whenever the Xil_In32() function is called ONLY when booting from non-volatile memory (QSPI flash or SD card). I have followed the prescribed process of making an FSBL, creating a boot image (with (bootloader)FSBL.elf, hw_wrapper.bit, main_project.elf) and programming the BOOT.bin file to flash memory successfully. The FSBL calls the 'ps7_init()' and ps7_post_config()' functions. My research shows that this issue revolves around enabling the level shifters, but as far as I can tell this occurs in the ps7_post_config() function. Any help would be appreciated. Details: Hardware: Zybo Trainer Board (Zynq 7010) Hardware peripherals: XADC Wizard, AXI GPIO Project: standalone C project Vivado 2017.2 Xilinx SDK 2017.2 OS: Windows 7 Enterprise SP1
  22. Arty hello world

    Hello to all, I'm a college student with a bit of arduino experience. I got ARTY because I have a course that requires learning the VHDL rudiments. (the choice of board was free, I hope I made a good choice!) My goal would be to start with a very simple project, maybe turn on some LEDs by pushing the buttons and getting familiar with the development environment. I am currently using Vivado 2017 and I have managed to have arty in the project board list. After that I do not know what to do, and I did not find a giuide for dummies that explained how to get to my goal. I have to use VHDL and for now my goal is to have a code as clean as possible and essential (also at the expense of not using all the potential of the board) I hope it is a not too complex and accessible request happy to start
  23. PikeOS project on ZC702

    Greetings all, I'm facing some issues in running my PikeOS project on zc702 board Following are some brief steps that i took to make PikeOS's project i selected a pikeOS integrated project, using devel-apex demo template Board Parameters Description: Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation kit. Architecture: arm Processor: v7hf Boot Strategy: uboot_dtb then in project Configuration, set path of binery to run on partition. on boot, it generate a file name, apex-devel-zynq-zc702-uboot in order to boot this project on board using sd card few more files are required. This is where i'm lost, can't figure how to generate those files, or where to find then. Hopefully Someone can help me. Thank You.
  24. NEXYS4 board cannot be detected

    Hi, I just installed vivado 2017.2 on my PC, running windows 7 Service Pack1 (64-bit). I connected my Nexys 4 board using the cable that comes with the board in the package. When I attempted to connect the board to my PC, by clicking Open Hardware Manager -> Open Target -> Auto Connect, in the Hardware window in vivado, it shows localhost(0), which means no device detected. I also get 2 warnings below: warning: cannot open library dpcomm.dll, first required symbol ftdimgr_lock, Digilent FTDI based JTAG cables cannot be supported warning: cannot open library djtg.dll, first required symbol DjtgGetPortCount, select Digilent JTAG cables cannot be supported I noticed a post in a non-English Digilent forum, in which someone else was experiencing the exact same issue. Please help. yy
  25. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!