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Found 4 results

  1. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the desired output but when I run the same through a program created on the host OS that is supposed to communicate with the PL it does not return a desired output or anywhere near it. I am attaching the IP core file, testbench file created in Vivado HLS and the C++ program running on the PS for communicating with the IP. Thank you in advance. core.cpp tb_core.cpp coprocessing.cpp
  2. Hello all. I'm a newbie to Vivado HLS (2018.3) and trying to add the Nexys 4 DDR board files in a new project, and it's not in the Device selection dialog list. I placed the board files in "Xilinx\Vivado\2018.3\data\boards\board_files" and it's there in Vivado, but not in Vivado HLS. How can I add the board files to Vivado HLS? Thank you!
  3. I am getting starting with Vivado_HLS 2018.2 and the zyboZ7-20 board. When attempting to create a project I find no default setting for the zyboZ7-20 board in the Vivado HLS "Part Selection". What is the recipe for giving the zyboZ7-20 board information to Vivado HLS? I see there are some examples using Vivado, but none using Vivado HLS. Being new at this, step-by-step would be very helpful. Thanks
  4. Hi,Just start learning HLS and XSDk. Currently I am working with number series. My goal is to print number series sequentially as for "N" times in Tera Terminal. While compiling the program codes, its returning values but it is not in sequence. Expected result:2, 4, 8, 16,32,64,128,256,512,1024, But i am getting : 4,8,16,256,128,1024,16,64,512,64, (not in order) For more details refer this [link]: void Numberseries1(ap_uint<32> seed, ap_uint<32> &dout) { #pragma HLS INTERFACE s_axilite port=seed bundle=a #pragma HLS INTERFACE s_axilite port=dout bundle=a #pragma HLS INTERFACE s_axilite port=return bundle=a ap_uint<32> reg[10]; int result=1; int i; for(i=0; i < 10;i++) #pragma HLS unroll factor=8 if (result<seed) { result *= 2; reg =result; dout= reg; } }