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Found 7 results

  1. Dear all, I am working with a video processing platform based on this project: https://www.hackster.io/adam-taylor/creating-a-zynq-or-fpga-based-image-processing-platform-e79394 I am using a Zybo Z7-20 and I am successful to make a simple passthrough buffer using VDMA. The project is described in the link above. However, when I create a project for a simple RGB2GRAY in Vivado HLS to insert block into the previous platform, I can't make it work (link for second project here: https://www.hackster.io/adam-taylor/using-hls-on-an-fpga-based-image-processing-platform-8f029f). Using linux I can't co-simulate C/RTL in Vivado HLS, but if I use windows this is not an issue. I don't really know why, but it is topic for another question. I generate the Vivado HLS block with ap_start hardwired to 1. Sometimes when I compile Vivado SDK I got some distortions with pixel flickering, but sometimes I can't even see any signals on the screen. I am really lost as I don't understand what is happening. Without the HLS block I have no problems, but after inserting it is completely messed up. I am enclosing the Vivado IP integrator block in PDF, as well the application code (hello.cpp) in the Xilinx SDK. What I also tried instead of hardwiring the HLS block (using #pragma HLS INTERFACE ap_ctrl_none port=return) was to assign ap_start to 1 using a constant or connecting to a GPIO and driving it to 1 in the Xilinx SDK. None methods worked. I am also attaching the whole project on this link: https://drive.google.com/file/d/1yM3upD4PuwHEXGZ_6M8O1-vZxLX5bIQP/view?usp=sharing. I am using Vivado 2018.3. Please, I really need help and I do appreciate any feedback on this issue. Thank you very much indeed. design_1.pdf hello.cpp
  2. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does typename P_T mean and how to define it in the header file. I am getting the following error with the current code that I have written C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h: In function 'void hls::Range(hls::Mat<ROWS, COLS, SRC1_T>&, hls::Mat<ROWS, COLS, SRC2_T>&, P_T, P_T) [with int ROWS = 720, int COLS = 1280, int SRC_T = 4096, int DST_T = 4096, P_T = hls::Scalar<3, unsigned char>]': ../../../yellow_threshold.cpp:24:32: instantiated from here C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h:1042:22: error: conversion from 'hls::Scalar<3, unsigned char>' to non-scalar type 'hls::_AP_T {aka ap_fixed<64, 32, (ap_q_mode)0u>}' requested make: *** [obj/yellow_threshold.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s) Please find the attached files for more details and suggest me how can I proceed. Thanks yellow_threshold.cpp yellow_threshold.h
  3. Hi , Does it possible to implement Python code on ARTY 7 board using Vivado HLS? If it is not, why it is possible with PYNQ board? Thanks
  4. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the desired output but when I run the same through a program created on the host OS that is supposed to communicate with the PL it does not return a desired output or anywhere near it. I am attaching the IP core file, testbench file created in Vivado HLS and the C++ program running on the PS for communicating with the IP. Thank you in advance. core.cpp tb_core.cpp coprocessing.cpp
  5. Hello all. I'm a newbie to Vivado HLS (2018.3) and trying to add the Nexys 4 DDR board files in a new project, and it's not in the Device selection dialog list. I placed the board files in "Xilinx\Vivado\2018.3\data\boards\board_files" and it's there in Vivado, but not in Vivado HLS. How can I add the board files to Vivado HLS? Thank you!
  6. I am getting starting with Vivado_HLS 2018.2 and the zyboZ7-20 board. When attempting to create a project I find no default setting for the zyboZ7-20 board in the Vivado HLS "Part Selection". What is the recipe for giving the zyboZ7-20 board information to Vivado HLS? I see there are some examples using Vivado, but none using Vivado HLS. Being new at this, step-by-step would be very helpful. Thanks
  7. Hi,Just start learning HLS and XSDk. Currently I am working with number series. My goal is to print number series sequentially as for "N" times in Tera Terminal. While compiling the program codes, its returning values but it is not in sequence. Expected result:2, 4, 8, 16,32,64,128,256,512,1024, But i am getting : 4,8,16,256,128,1024,16,64,512,64, (not in order) For more details refer this [link]: https://forums.xilinx.com/t5/Welcome-Join/Returning-only-Last-value-in-XSDK-From-HLS-IP-Instead-of-series/td-p/767236 void Numberseries1(ap_uint<32> seed, ap_uint<32> &dout) { #pragma HLS INTERFACE s_axilite port=seed bundle=a #pragma HLS INTERFACE s_axilite port=dout bundle=a #pragma HLS INTERFACE s_axilite port=return bundle=a ap_uint<32> reg[10]; int result=1; int i; for(i=0; i < 10;i++) #pragma HLS unroll factor=8 if (result<seed) { result *= 2; reg =result; dout= reg; } }