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Found 7 results

  1. Dear all, I am working with a video processing platform based on this project: https://www.hackster.io/adam-taylor/creating-a-zynq-or-fpga-based-image-processing-platform-e79394 I am using a Zybo Z7-20 and I am successful to make a simple passthrough buffer using VDMA. The project is described in the link above. However, when I create a project for a simple RGB2GRAY in Vivado HLS to insert block into the previous platform, I can't make it work (link for second project here: https://www.hackster.io/adam-taylor/using-hls-on-an-fpga-based-image-processing-platform-8f029f). U
  2. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does ty
  3. Hi , Does it possible to implement Python code on ARTY 7 board using Vivado HLS? If it is not, why it is possible with PYNQ board? Thanks
  4. Hi, I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. When I run the c_simulation through Vivado hls it gives me the d
  5. Hello all. I'm a newbie to Vivado HLS (2018.3) and trying to add the Nexys 4 DDR board files in a new project, and it's not in the Device selection dialog list. I placed the board files in "Xilinx\Vivado\2018.3\data\boards\board_files" and it's there in Vivado, but not in Vivado HLS. How can I add the board files to Vivado HLS? Thank you!
  6. I am getting starting with Vivado_HLS 2018.2 and the zyboZ7-20 board. When attempting to create a project I find no default setting for the zyboZ7-20 board in the Vivado HLS "Part Selection". What is the recipe for giving the zyboZ7-20 board information to Vivado HLS? I see there are some examples using Vivado, but none using Vivado HLS. Being new at this, step-by-step would be very helpful. Thanks
  7. Hi,Just start learning HLS and XSDk. Currently I am working with number series. My goal is to print number series sequentially as for "N" times in Tera Terminal. While compiling the program codes, its returning values but it is not in sequence. Expected result:2, 4, 8, 16,32,64,128,256,512,1024, But i am getting : 4,8,16,256,128,1024,16,64,512,64, (not in order) For more details refer this [link]: https://forums.xilinx.com/t5/Welcome-Join/Returning-only-Last-value-in-XSDK-From-HLS-IP-Instead-of-series/td-p/767236 void Numberseries1(ap_uint<32> seed, ap_uint<32>