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Showing results for tags 'vivado 2019.2'.
I want to use PmodIOXP to allow both PmodAQS and PmodHYGRO to be connected into the same port in Zybo Z720. However, I do not know how to write my block design in Vivado since there is no IP for PmodIOXP in the vivado-library. Also, what kind of C++ code should I write in my Vitis after I exported my vivado file into Vitis
Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.