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I'm trying to integrate a custom IP module (AXI4 peripheral) with the Vivado IP Integrator flow on the Arty-A7 board. I've followed the tutorial outlined here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start I am able to successfully generate a bitstream - my PWM signals should be wired out to the PMOD JB connector. However, nothing works once I try to launch an application from within SDK. Even something as simple as "Hello World" fails to run. The board support package, libraries, and applications all compile without issue. The kicker is that as soon as I revert back to the design WITHOUT the custom IP module, everything works fine and I can run applications from within SDK. Below are screenshots of my block diagram and constraints file. The constraints file only contains the additional information required for the PWM signals, assuming all the rest of the constraints are pulled in from the board file like they are when the custom IP module is not part of the design. Thoughts??? Using Vivado 2017.4

Hello. I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe). Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export. When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files. In reference to error [Synth 8-5809] I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to change it. https://www.xilinx.com/support/answers/68421.html Regarding the second error [synth 8-285] I found this, which claims the problem was in 2016.2, but still appears, so I am skeptical of this solution. Was the default changed back to OOC per IP with 2017.4? I am not sure what generate_target means or does, or when it is processed in the GUI workflow. So I am not sure when to do this in the workflow or what it will do. https://www.xilinx.com/support/answers/68238.html In Vivado 2016.3 there was a change to the default BD generation mode. The default was changed from Global to Out of Context (OOC) per IP. You will not typically see this problem when migrating an existing project because the migration script will maintain the existing generation mode setting. However, in a scripted flow where the entire project or design is being recreated, the new default settings would apply unless explicitly changed. Additionally, the "OOC per IP" BD generation is not allowed in non-project mode. Therefore, starting in Vivado 2016.3, if you are using a scripted non-project mode, you will need to set the BD generation back to global. To do this, set the synth_checkpoint_mode to None (Global synthesis) before generating targets. For example: set_property synth_checkpoint_mode None [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] generate_target all [get_files ./proj.srcs/sources_1/bd/my_bd/my_bd.bd] Can someone assist me in this upgrade? I imagine Digilent will be upgrading their example projects at some point. Now would be a great time! Thank you!