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Showing results for tags 'vivado 2017.4'.
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I'm trying to integrate a custom IP module (AXI4 peripheral) with the Vivado IP Integrator flow on the Arty-A7 board. I've followed the tutorial outlined here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start I am able to successfully generate a bitstream - my PWM signals should be wired out to the PMOD JB connector. However, nothing works once I try to launch an application from within SDK. Even something as simple as "Hello World" fails to run. The board support package, libraries, and applications all compile without issu
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Hello. I have developed a Microblaze project based on a Digilent Vivado 2016.4 project for the Arty board that I downloaded a year ago. (microblaze server I believe). Everything works in Vivado 2016.4, I can go through the entire implementation to bitstream and SDK export. When upgrading to Vivado 2017.4, I get these errors referring to some encrypted files. In reference to error [Synth 8-5809] I have found this not-to-helpful answer record, referring to FLIT width in an XHMC IP that I dont think is eve nin the project, with no information on how to
